Welcome![Sign In][Sign Up]
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: shuzizhong Download
  • Category:
  • Windows Kernel
  • Tags:
  • File Size:
  • 17kb
  • Update:
  • 2012-11-26
  • Downloads:
  • 0 Times
  • Uploaded by:
  • gyxin87
 Description: The digital clock can achieve normal timing, support for 12 hours and 24 hours two timing mode switch allows the user to manually tune and the whole hour. Systems external to provide users with two keys: the function key and adjust the key function keys for function selection and adjustment button for the relevant time to adjust the power system began timing, if you click a function key, adjust the hour mode, and then once for the tone patterns, and then enter 12/24 hour mode select Settings, and then restored to normal timekeeping. in normal time status, the user can select 12 or 24 hours timing sixth of the way, the bottom right of the small digital tube light 12 hour mode, light 24 hours. The whole point of time when the dot of six digital tube light. Button to enter the school when the second digital tube light, that now the hour set Similarly, when the school sub-state, the fourth digital control points will be bright, said that now are minute set.
 Downloaders recently: [More information of uploader gyxin87]
 To Search:
File list (Check if you may need any files):
数字钟.docx
    

CodeBus www.codebus.net