Description: module alu (ina, inb, ALU_BUS, S, cout, y, clk) input [7:0] ina input [7:0] inb input ALU_BUS, clk input [2:0] S output cout output [7:0] y reg cout reg [7:0] y always @ (posedge clk) begin if (ALU_BUS) begin case (S) 3' b000: {cout, y} = ina+inb 3' b001 : {cout, y} = ina-inb 3' b010: {cout, y} = ina* inb 3' b011: {cout, y} = ina/inb 3' b100: y = ina & & inb 3' b101 : y = ina | | inb 3' b110: y = ~ inb 3' b111: y = ina ^ inb default: y = 8' b00000000 endcase end else begin y = 8' bZZZZZZZZ end end endmodule
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alu\alu.asm.rpt
...\alu.bsf
...\alu.done
...\alu.fit.rpt
...\alu.fit.smsg
...\alu.fit.summary
...\alu.flow.rpt
...\alu.map.rpt
...\alu.map.summary
...\alu.pin
...\alu.pof
...\alu.qpf
...\alu.qsf
...\alu.qws
...\alu.rar
...\alu.sim.rpt
...\alu.sof
...\alu.tan.rpt
...\alu.tan.summary
...\alu.v
...\alu.vwf
...\db\add_sub_0ec.tdf
...\..\add_sub_1ec.tdf
...\..\add_sub_2ec.tdf
...\..\add_sub_3ec.tdf
...\..\add_sub_4ec.tdf
...\..\add_sub_5ec.tdf
...\..\add_sub_6ac.tdf
...\..\add_sub_6ec.tdf
...\..\add_sub_7ec.tdf
...\..\add_sub_ioh.tdf
...\..\add_sub_qph.tdf
...\..\alt_u_div_gpe.tdf
...\..\alu.asm.qmsg
...\..\alu.cbx.xml
...\..\alu.cmp.cdb
...\..\alu.cmp.hdb
...\..\alu.cmp.kpt
...\..\alu.cmp.logdb
...\..\alu.cmp.rdb
...\..\alu.cmp.tdb
...\..\alu.cmp0.ddb
...\..\alu.dbp
...\..\alu.db_info
...\..\alu.eco.cdb
...\..\alu.eds_overflow
...\..\alu.fit.qmsg
...\..\alu.fnsim.cdb
...\..\alu.fnsim.hdb
...\..\alu.fnsim.qmsg
...\..\alu.hier_info
...\..\alu.hif
...\..\alu.map.cdb
...\..\alu.map.hdb
...\..\alu.map.logdb
...\..\alu.map.qmsg
...\..\alu.pre_map.cdb
...\..\alu.pre_map.hdb
...\..\alu.psp
...\..\alu.pss
...\..\alu.rtlv.hdb
...\..\alu.rtlv_sg.cdb
...\..\alu.rtlv_sg_swap.cdb
...\..\alu.sgdiff.cdb
...\..\alu.sgdiff.hdb
...\..\alu.signalprobe.cdb
...\..\alu.sim.hdb
...\..\alu.sim.qmsg
...\..\alu.sim.rdb
...\..\alu.sim.vwf
...\..\alu.sld_design_entry.sci
...\..\alu.sld_design_entry_dsc.sci
...\..\alu.syn_hier_info
...\..\alu.tan.qmsg
...\..\lpm_divide_g6m.tdf
...\..\mult_nl01.tdf
...\..\sign_div_unsign_fkh.tdf
...\..\wed.zsf
...\db
alu
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