Description: The VHDL language RISC_CPU, is divided into eight basic components of modular construction, respectively, the clock generator, the instruction register, accumulator, arithmetic and logic unit, the data controller, the state controller, the program counter and address multiplexer
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RISC_CPU\accumulator.vhd
........\addr.vhd
........\addr_decode.vhd
........\alu.vhd
........\clkchange.vhd
........\clk_gen.vhd
........\counter.vhd
........\cpumain.vhd
........\datactl.vhd
........\instruction_register.vhd
........\machine.vhd
........\machinectl.vhd
........\ram.vhd
........\rom.vhd
RISC_CPU
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