Description: generte sin wave, the frequence is 1Hz,FPGA processing module is required to work various parts of the system clock signal from the input clock signal by dividing the system clock input signal should meet the requirements of the input pulse
To Search:
File list (Check if you may need any files):
SIN_NEW1Hz\bcd_78.vhd.bak
..........\sin.map.rpt
..........\bcd_78.vhd
..........\sin.csv
..........\sin.qpf
..........\sin.qsf
..........\freqin.bsf
..........\sin.bdf
..........\add20b.bsf
..........\sin.done
..........\reg20.bsf
..........\freqin.vhd
..........\sin256.vhd
..........\sin.map.summary
..........\sin.flow.rpt
..........\sin.fit.rpt
..........\sin.sim.rpt
..........\sin.qws
..........\sin256.inc
..........\sin256.cmp
..........\mult.vhd
..........\sin.pin
..........\sin.fit.smsg
..........\sin.fit.summary
..........\freq.bsf
..........\FANGBO.mif
..........\fangbo.vhd
..........\sin256.bsf
..........\sin.sof
..........\sin.pof
..........\sin256_waveforms.html
..........\sin256.qip
..........\sin.tan.summary
..........\sin256_wave0.jpg
..........\fangbo.inc
..........\mult.inc
..........\sin.vwf
..........\fangbo_waveforms.html
..........\fangbo_wave0.jpg
..........\sin.asm.rpt
..........\amp.vhd
..........\mult_waveforms.html
..........\mult_wave0.jpg
..........\mult.cmp
..........\sin.dpf
..........\mult.bsf
..........\mult_inst.vhd
..........\mult.qip
..........\sin256_inst.vhd
..........\fangbo.cmp
..........\fangbo.bsf
..........\fangbo.qip
..........\sin256.mif
..........\fangbo_inst.vhd
..........\sanjiaobo_waveforms.html
..........\sanjiaobo.mif
..........\sanjiaobo_wave0.jpg
..........\signalchoose.vhd.bak
..........\sanjiaobo.vhd
..........\sanjiaobo.inc
..........\sanjiaobo.cmp
..........\sanjiaobo.bsf
..........\sanjiaobo_inst.vhd
..........\sanjiaobo.qip
..........\signalchoose.vhd
..........\signalchoose.bsf
..........\pll_waveforms.html
..........\pll_wave0.jpg
..........\pll.vhd
..........\pll.ppf
..........\pll.inc
..........\pll.cmp
..........\pll.bsf
..........\pll_inst.vhd
..........\pll.qip
..........\sin.cdf
..........\reg20.vhd.bak
..........\reg20.vhd
..........\add20b.vhd.bak
..........\add20b.vhd
..........\db\sin.db_info
..........\..\sin.sld_design_entry.sci
..........\..\sin.eco.cdb
..........\..\mult_3qp.tdf
..........\..\prev_cmp_sin.map.qmsg
..........\..\altsyncram_6071.tdf
..........\..\prev_cmp_sin.qmsg
..........\..\wed.wsf
..........\..\mult_b9n.tdf
..........\..\sin.sim.cvwf
..........\..\prev_cmp_sin.sim.qmsg
..........\..\prev_cmp_sin.fit.qmsg
..........\..\add_sub_9ch.tdf
..........\..\add_sub_4ch.tdf
..........\..\prev_cmp_sin.tan.qmsg
..........\..\altsyncram_le71.tdf
..........\..\altsyncram_c471.tdf
..........\..\prev_cmp_sin.asm.qmsg
..........\..\mult_bqp.tdf
..........\incremental_db\README
Download