新建文件夹 (3)\FPGA_Project1.PrjFpg
..............\FPGA_Project1.PrjFpgStructure
..............\History\FPGA_Project1.~(1).PrjFpg.Zip
..............\.......\FPGA_Project1.~(2).PrjFpg.Zip
..............\.......\FPGA_Project1.~(3).PrjFpg.Zip
..............\.......\Sheet1.~(1).SchDoc.Zip
..............\.......\Sheet1.~(2).SchDoc.Zip
..............\.......\Sheet1.~(3).SchDoc.Zip
..............\.......\Sheet1.~(4).SchDoc.Zip
..............\.......\Sheet1.~(5).SchDoc.Zip
..............\.......\Sheet1.~(6).SchDoc.Zip
..............\.......\Sheet1.~(7).SchDoc.Zip
..............\.......\Sheet1.~(8).SchDoc.Zip
..............\.......\VHDL1.~(1).Vhd.Zip
..............\.......\VHDL1.~(10).Vhd.Zip
..............\.......\VHDL1.~(11).Vhd.Zip
..............\.......\VHDL1.~(12).Vhd.Zip
..............\.......\VHDL1.~(13).Vhd.Zip
..............\.......\VHDL1.~(14).Vhd.Zip
..............\.......\VHDL1.~(15).Vhd.Zip
..............\.......\VHDL1.~(16).Vhd.Zip
..............\.......\VHDL1.~(17).Vhd.Zip
..............\.......\VHDL1.~(18).Vhd.Zip
..............\.......\VHDL1.~(19).Vhd.Zip
..............\.......\VHDL1.~(2).Vhd.Zip
..............\.......\VHDL1.~(20).Vhd.Zip
..............\.......\VHDL1.~(21).Vhd.Zip
..............\.......\VHDL1.~(22).Vhd.Zip
..............\.......\VHDL1.~(23).Vhd.Zip
..............\.......\VHDL1.~(24).Vhd.Zip
..............\.......\VHDL1.~(25).Vhd.Zip
..............\.......\VHDL1.~(26).Vhd.Zip
..............\.......\VHDL1.~(27).Vhd.Zip
..............\.......\VHDL1.~(28).Vhd.Zip
..............\.......\VHDL1.~(29).Vhd.Zip
..............\.......\VHDL1.~(3).Vhd.Zip
..............\.......\VHDL1.~(30).Vhd.Zip
..............\.......\VHDL1.~(31).Vhd.Zip
..............\.......\VHDL1.~(32).Vhd.Zip
..............\.......\VHDL1.~(33).Vhd.Zip
..............\.......\VHDL1.~(34).Vhd.Zip
..............\.......\VHDL1.~(35).Vhd.Zip
..............\.......\VHDL1.~(36).Vhd.Zip
..............\.......\VHDL1.~(37).Vhd.Zip
..............\.......\VHDL1.~(38).Vhd.Zip
..............\.......\VHDL1.~(39).Vhd.Zip
..............\.......\VHDL1.~(4).Vhd.Zip
..............\.......\VHDL1.~(40).Vhd.Zip
..............\.......\VHDL1.~(5).Vhd.Zip
..............\.......\VHDL1.~(6).Vhd.Zip
..............\.......\VHDL1.~(7).Vhd.Zip
..............\.......\VHDL1.~(8).Vhd.Zip
..............\.......\VHDL1.~(9).Vhd.Zip
..............\ProjectOutputs\Default - All Constraints\FPGA_Project1.bfl
..............\..............\.........................\fpga_project1.bgn
..............\..............\.........................\fpga_project1.bit
..............\..............\.........................\fpga_project1.bld
..............\..............\.........................\FPGA_Project1.edf
..............\..............\.........................\FPGA_Project1.FlwCmp
..............\..............\.........................\FPGA_Project1.mof
..............\..............\.........................\FPGA_Project1.mpf
..............\..............\.........................\fpga_project1.ncd
..............\..............\.........................\fpga_project1.ngd
..............\..............\.........................\FPGA_Project1.npl
..............\..............\.........................\fpga_project1.pad
..............\..............\.........................\fpga_project1.par
..............\..............\.........................\fpga_project1.rbt
..............\..............\.........................\fpga_project1.twr
..............\..............\.........................\FPGA_Project1.ucf
..............\..............\.........................\fpga_project1.xpi
..............\..............\.........................\FPGA_Project1.~.bit
..............\..............\.........................\FPGA_Project1.~.ncd
..............\..............\.........................\FPGA_Project1.~.ngd
..............\..............\.........................\FPGA_Project1_BUILD.UCF
..............\..............\.........................\fpga_project1_cclk.bgn
..............\..............\.........................\fpga_project1_cclk.bit
..............\..............\....................