Description: there are two madules,both of them contain an inout port,As module1 sends out data on its inout port,the inout port on second module would be an input,and vice versa
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File list (Check if you may need any files):
inout_test\inout_test\0inout_test.mgf
..........\..........\1inout_test.mgf
..........\..........\3inout_test.mgf
..........\..........\bde.set
..........\..........\compilation.order
..........\..........\......e\contents.lib~inout_test
..........\..........\.......\inout_test.epr
..........\..........\.......\inout_test.erf
..........\..........\.......\inout_test.opt
..........\..........\.......\inout_test.opv
..........\..........\.......\sources.sth
..........\..........\.......\vcp_cmd.log
..........\..........\compile
..........\..........\compile.cfg
..........\..........\Edfmap.ini
..........\..........\elaboration.log
..........\..........\inout_test.adf
..........\..........\inout_test.LIB
..........\..........\inout_test.rlb
..........\..........\inout_test.wsp
..........\..........\inout_test_0.rep
..........\..........\log\console.log
..........\..........\log
..........\..........\projlib.cfg
..........\..........\slp\2.ff
..........\..........\...\ext.gen
..........\..........\...\logs\link_err.log
..........\..........\...\....\tmp.log
..........\..........\...\logs
..........\..........\...\slp_model.dll
..........\..........\...\slp_model.info
..........\..........\...\slp_model2.info
..........\..........\...\spi.gen
..........\..........\slp
..........\..........\.rc\inout_test.v
..........\..........\...\TestBench\inout_test_TB.v
..........\..........\...\.........\inout_test_TB_runtest.do
..........\..........\...\.........\inout_test_TB_settings.txt
..........\..........\...\TestBench
..........\..........\...\wave.asdb
..........\..........\src
..........\..........\synthesis.order
..........\inout_test
..........\library.cfg
..........\mod1\0mod1.mgf
..........\....\1mod1.mgf
..........\....\3mod1.mgf
..........\....\bde.set
..........\....\compilation.order
..........\....\......e\contents.lib~mod1
..........\....\.......\mod1.epr
..........\....\.......\mod1.erf
..........\....\.......\mod1.opt
..........\....\.......\mod1.opv
..........\....\.......\run_cdebug.do
..........\....\.......\sources.sth
..........\....\.......\vcp_cmd.log
..........\....\compile
..........\....\compile.cfg
..........\....\Edfmap.ini
..........\....\elaboration.log
..........\....\log\console.log
..........\....\...\vsimsa.log
..........\....\log
..........\....\mod1.adf
..........\....\mod1.LIB
..........\....\mod1.rlb
..........\....\mod1.wsp
..........\....\mod1_0.rep
..........\....\projlib.cfg
..........\....\slp\2.ff
..........\....\...\ext.gen
..........\....\...\logs\link_err.log
..........\....\...\....\tmp.log
..........\....\...\logs
..........\....\...\slp_model.dll
..........\....\...\slp_model.info
..........\....\...\slp_model2.info
..........\....\...\spi.gen
..........\....\slp
..........\....\.rc\inout_test.asdb
..........\....\...\inout_test.awc
..........\....\...\mod_a.v
..........\....\...\mod_top.v
..........\....\...\TestBench\mod_top_TB.v
..........\....\...\.........\mod_top_TB_runtest.do
..........\....\...\.........\mod_top_TB_settings.txt
..........\....\...\TestBench
..........\....\...\vsimsa.cfg
..........\....\...\wave.asdb
..........\....\src
..........\....\synthesis.order
..........\mod1
..........\test4.aws
..........\test4.wsw
inout_test
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