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VHDL-FPGA-Verilog
Title:
adder
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Category:
VHDL-FPGA-Verilog
Tags:
[VHDL]
[源码]
File Size:
2kb
Update:
2012-11-26
Downloads:
0 Times
Uploaded by:
raul_shao
Description:
Design of a 16 x 16 pipelined multiplier. Multiplier by 16 x 16 carry save array ( Carry-save ). The last line of the partial product generation unit requires use of carry lookahead.
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(Check if you may need any files):
adder4bit.v adder16bit.v full_adder.v half_adder.v line.v mult16bit.v testbench.v
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