1602_CLOCK\1602_CLOCK.asm.rpt
..........\1602_CLOCK.cdf
..........\1602_CLOCK.done
..........\1602_CLOCK.dpf
..........\1602_CLOCK.eda.rpt
..........\1602_CLOCK.fit.rpt
..........\1602_CLOCK.fit.smsg
..........\1602_CLOCK.fit.summary
..........\1602_CLOCK.flow.rpt
..........\1602_CLOCK.map.rpt
..........\1602_CLOCK.map.smsg
..........\1602_CLOCK.map.summary
..........\1602_CLOCK.pin
..........\1602_CLOCK.pof
..........\1602_CLOCK.qpf
..........\1602_CLOCK.qsf
..........\1602_CLOCK.sof
..........\1602_CLOCK.tan.rpt
..........\1602_CLOCK.tan.summary
..........\1602_CLOCK.v
..........\1602_CLOCK.v.bak
..........\1602_CLOCK_assignment_defaults.qdf
..........\1602_CLOCK_description.txt
..........\1602_CLOCK_nativelink_simulation.rpt
..........\db\1602_CLOCK.db_info
..........\..\1602_CLOCK.sld_design_entry.sci
..........\..\logic_util_heursitic.dat
..........\..\prev_cmp_1602_CLOCK.qmsg
..........\incremental_db\compiled_partitions\1602_CLOCK.db_info
..........\..............\...................\1602_CLOCK.root_partition.cmp.dfp
..........\..............\...................\1602_CLOCK.root_partition.cmp.kpt
..........\..............\...................\1602_CLOCK.root_partition.cmp.logdb
..........\..............\...................\1602_CLOCK.root_partition.map.dpi
..........\..............\...................\1602_CLOCK.root_partition.map.kpt
..........\..............\README
..........\simulation\modelsim\1602_CLOCK.sft
..........\..........\........\1602_CLOCK.vo
..........\..........\........\1602_CLOCK_modelsim.xrf
..........\..........\........\1602_CLOCK_run_msim_gate_verilog.do
..........\..........\........\1602_CLOCK_run_msim_rtl_verilog.do
..........\..........\........\1602_CLOCK_run_msim_rtl_verilog.do.bak
..........\..........\........\1602_CLOCK_run_msim_rtl_verilog.do.bak1
..........\..........\........\1602_CLOCK_run_msim_rtl_verilog.do.bak2
..........\..........\........\1602_CLOCK_run_msim_rtl_verilog.do.bak3
..........\..........\........\1602_CLOCK_run_msim_rtl_verilog.do.bak4
..........\..........\........\1602_CLOCK_run_msim_rtl_verilog.do.bak5
..........\..........\........\1602_CLOCK_run_msim_rtl_verilog.do.bak6
..........\..........\........\1602_CLOCK_run_msim_rtl_verilog.do.bak7
..........\..........\........\1602_CLOCK_v.sdo
..........\..........\........\1602_CLOCK_v.sdo_typ.csd
..........\..........\........\CLOCK_1602.vt
..........\..........\........\CLOCK_1602.vt.bak
..........\..........\........\gate_work\@c@l@o@c@k_1602\verilog.prw
..........\..........\........\.........\...............\verilog.psm
..........\..........\........\.........\...............\_primary.dat
..........\..........\........\.........\...............\_primary.dbs
..........\..........\........\.........\...............\_primary.vhd
..........\..........\........\.........\..............._vlg_tst\verilog.prw
..........\..........\........\.........\.......................\verilog.psm
..........\..........\........\.........\.......................\_primary.dat
..........\..........\........\.........\.......................\_primary.dbs
..........\..........\........\.........\.......................\_primary.vhd
..........\..........\........\.........\_info
..........\..........\........\.........\_vmake
..........\..........\........\modelsim.ini
..........\..........\........\msim_transcript
..........\..........\........\rtl_work\@c@l@o@c@k_1602\verilog.prw
..........\..........\........\........\...............\verilog.psm
..........\..........\........\........\...............\_primary.dat
..........\..........\........\........\...............\_primary.dbs
..........\..........\........\........\...............\_primary.vhd
..........\..........\........\........\..............._vlg_tst\verilog.prw
..........\..........\........\........\.......................\verilog.psm
..........\..........\........\........\.......................\_primary.dat
..........\..........\........\........\.......................\_primary.dbs
..........\..........\........\........\.......................\_primary.vhd
.........