《Verilog HDL数字控制系统设计实例》-冼进-源代码\第1章\subtracter_1\subtracter_1.qpf
...............................................\.....\............\subtracter_1.qsf
...............................................\.....\............\db\subtracter_1.db_info
...............................................\.....\............\..\subtracter_1.cmp.hdb
...............................................\.....\............\..\subtracter_1.cmp.rdb
...............................................\.....\............\..\subtracter_1.sim.qmsg
...............................................\.....\............\..\subtracter_1.hif
...............................................\.....\............\..\subtracter_1.sim.hdb
...............................................\.....\............\..\subtracter_1.cmp.ddb
...............................................\.....\............\..\subtracter_1.sim.vwf
...............................................\.....\............\..\subtracter_1.sim.rdb
...............................................\.....\............\..\subtracter_1.hier_info
...............................................\.....\............\..\subtracter_1.sld_design_entry.sci
...............................................\.....\............\..\subtracter_1.eco.cdb
...............................................\.....\............\..\subtracter_1.psp
...............................................\.....\............\..\subtracter_1.syn_hier_info
...............................................\.....\............\..\subtracter_1_cmp.qrpt
...............................................\.....\............\..\subtracter_1.eds_overflow
...............................................\.....\............\..\subtracter_1_sim.qrpt
...............................................\.....\............\..\subtracter_1.map.qmsg
...............................................\.....\............\..\subtracter_1.rtlv_sg.cdb
...............................................\.....\............\..\subtracter_1.rtlv.hdb
...............................................\.....\............\..\subtracter_1.rtlv_sg_swap.cdb
...............................................\.....\............\..\subtracter_1.pre_map.hdb
...............................................\.....\............\..\subtracter_1.pre_map.cdb
...............................................\.....\............\..\subtracter_1.sgdiff.cdb
...............................................\.....\............\..\subtracter_1.sgdiff.hdb
...............................................\.....\............\..\subtracter_1.sld_design_entry_dsc.sci
...............................................\.....\............\..\subtracter_1.map.cdb
...............................................\.....\............\..\subtracter_1.map.hdb
...............................................\.....\............\..\subtracter_1.fit.qmsg
...............................................\.....\............\..\subtracter_1.asm.qmsg
...............................................\.....\............\..\subtracter_1.tan.qmsg
...............................................\.....\............\..\subtracter_1.cmp.tdb
...............................................\.....\............\..\subtracter_1.cmp0.ddb
...............................................\.....\............\..\subtracter_1.cmp.cdb
...............................................\.....\............\subtracter_1.map.eqn
...............................................\.....\............\subtracter_1.map.rpt
...............................................\.....\............\subtracter_1.flow.rpt
...............................................\.....\............\subtracter_1.map.summary
...............................................\.....\............\subtracter_1.fit.eqn
...............................................\.....\............\subtracter_1.pin
...............................................\.....\............\subtracter_1.fit.rpt
...............................................\.....\............\subtracter_1.fit.summary
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