spi_controller
..............\bench.vcd
..............\chart
..............\.....\Thumbs.db
..............\.....\图6-11.bmp
..............\.....\图6-12.bmp
..............\.....\图6-13.bmp
..............\.....\图6-14.bmp
..............\.....\图6-17.bmp
..............\.....\图6-18.bmp
..............\.....\图6-19.bmp
..............\.....\图6-7.bmp
..............\spi_clgen.v
..............\spi_controller.cr.mti
..............\spi_controller.mpf
..............\spi_defines.v
..............\spi_shift.v
..............\spi_slave_model.v
..............\spi_top.v
..............\tb_spi_top.v
..............\timescale.v
..............\transcript
..............\vsim.wlf
..............\wave
..............\....\spi_clgen.bmp
..............\....\spi_shift.bmp
..............\....\spi_slave_model.bmp
..............\....\spi_top.bmp
..............\....\tb_spi_top.bmp
..............\....\Thumbs.db
..............\....\wb_master_model.bmp
..............\wb_master_model.v
..............\work
..............\....\spi_clgen
..............\....\.........\verilog.asm
..............\....\.........\_primary.dat
..............\....\.........\_primary.vhd
..............\....\spi_shift
..............\....\.........\verilog.asm
..............\....\.........\_primary.dat
..............\....\.........\_primary.vhd
..............\....\spi_slave_model
..............\....\...............\verilog.asm
..............\....\...............\_primary.dat
..............\....\...............\_primary.vhd
..............\....\spi_top
..............\....\.......\verilog.asm
..............\....\.......\_primary.dat
..............\....\.......\_primary.vhd
..............\....\tb_spi_top
..............\....\..........\verilog.asm
..............\....\..........\_primary.dat
..............\....\..........\_primary.vhd
..............\....\wb_master_model
..............\....\...............\verilog.asm
..............\....\...............\_primary.dat
..............\....\...............\_primary.vhd
..............\....\_info