Description: The design of an increment and decrement of eight two-way loop counter.
(1) asynchronous reset, the reset start counting from the last jump of the first valid clock edge If the dir = 1, then the counting up, otherwise,
Count down.
(2) the output count of 8
(3) conduct a comprehensive simulation of the circuit.
(4) The design module is called:
counter8b_updown (count, clk, reset, dir)
The test platform module named:
tb_counter8b_updown ()
To Search:
File list (Check if you may need any files):
seg_gen.v
shift_register_4b.v
tb_shift_register_4b.v
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