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Title: DDS_Lock_In_Amplifier Download
 Description: Using phase-locked loop, direct data integration technologies to create works in the FPGA
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DDS_COSTAS锁相环中\dds_20071031\dds.cr.mti
..................\............\dds.mpf
..................\............\dds.prd
..................\............\dds.prj
..................\............\dds.v
..................\............\dds_tb.v
..................\............\rev_1\dds.areasrr
..................\............\.....\dds.edn
..................\............\.....\dds.htm
..................\............\.....\dds.sap
..................\............\.....\dds.sdf
..................\............\.....\dds.srd
..................\............\.....\dds.srm
..................\............\.....\dds.srr
..................\............\.....\dds.srs
..................\............\.....\dds.tap
..................\............\.....\dds.tlg
..................\............\.....\dds_sdc.sdc
..................\............\.....\syntmp\dds.plg
..................\............\.....\......\dds_flink.htm
..................\............\.....\......\dds_srr.htm
..................\............\.....\......\dds_toc.htm
..................\............\.....\......\sap.log
..................\............\rom_syn.v
..................\............\sin.mif
..................\............\transcript
..................\............\vsim.wlf
..................\............\wave.do
..................\............\.ork\accumulator\_primary.dat
..................\............\....\...........\_primary.dbs
..................\............\....\...........\_primary.vhd
..................\............\....\dds\verilog.asm
..................\............\....\...\_primary.dat
..................\............\....\...\_primary.dbs
..................\............\....\...\_primary.vhd
..................\............\....\..._tb\verilog.asm
..................\............\....\......\_primary.dat
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..................\............\....\rom\verilog.asm
..................\............\....\...\_primary.dat
..................\............\....\...\_primary.dbs
..................\............\....\...\_primary.vhd
..................\............\....\..._altsyncram\verilog.asm
..................\............\....\..............\_primary.dat
..................\............\....\..............\_primary.dbs
..................\............\....\..............\_primary.vhd
..................\............\....\_info
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..................\............\....\.....\vlogrd14mb
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..................\............\....\.....\vlogy27i5a
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..................\............\....\.....\vlogz592db
..................\............\rev_1\syntmp
..................\............\work\accumulator
..................\............\....\dds
..................\............\....\dds_tb
..................\............\....\rom
..................\............\....\rom_altsyncram
..................\............\....\_temp
..................\............\rev_1
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