Welcome![Sign In][Sign Up]
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: CLOCK_fpga Download
 Description: 电子钟,由fpga实现, clock for fpga
 Downloaders recently: [More information of uploader deng]
 To Search:
File list (Check if you may need any files):
CLOCK
.....\CLOCK.asm.rpt
.....\CLOCK.done
.....\CLOCK.dpf
.....\CLOCK.fit.rpt
.....\CLOCK.fit.summary
.....\CLOCK.flow.rpt
.....\CLOCK.jed
.....\CLOCK.map.rpt
.....\CLOCK.map.smsg
.....\CLOCK.map.summary
.....\CLOCK.pin
.....\CLOCK.pof
.....\CLOCK.qpf
.....\CLOCK.qsf
.....\CLOCK.qws
.....\CLOCK.tan.rpt
.....\CLOCK.tan.summary
.....\CLOCK.txt
.....\CLOCK.v
.....\CLOCK.v.bak
.....\db
.....\..\add_sub_3kh.tdf
.....\..\add_sub_9ph.tdf
.....\..\CLOCK.asm.qmsg
.....\..\CLOCK.cbx.xml
.....\..\CLOCK.cmp.cdb
.....\..\CLOCK.cmp.hdb
.....\..\CLOCK.cmp.logdb
.....\..\CLOCK.cmp.rdb
.....\..\CLOCK.cmp.tdb
.....\..\CLOCK.cmp0.ddb
.....\..\CLOCK.db_info
.....\..\CLOCK.eco.cdb
.....\..\CLOCK.fit.qmsg
.....\..\CLOCK.hier_info
.....\..\CLOCK.hif
.....\..\CLOCK.map.cdb
.....\..\CLOCK.map.hdb
.....\..\CLOCK.map.logdb
.....\..\CLOCK.map.qmsg
.....\..\CLOCK.pre_map.cdb
.....\..\CLOCK.pre_map.hdb
.....\..\CLOCK.rtlv.hdb
.....\..\CLOCK.rtlv_sg.cdb
.....\..\CLOCK.rtlv_sg_swap.cdb
.....\..\CLOCK.sgdiff.cdb
.....\..\CLOCK.sgdiff.hdb
.....\..\CLOCK.sld_design_entry.sci
.....\..\CLOCK.sld_design_entry_dsc.sci
.....\..\CLOCK.syn_hier_info
.....\..\CLOCK.tan.qmsg
.....\..\CLOCK.tis_db_list.ddb
.....\..\CLOCK.tmw_info
.....\..\prev_cmp_CLOCK.asm.qmsg
.....\..\prev_cmp_CLOCK.fit.qmsg
.....\..\prev_cmp_CLOCK.map.qmsg
.....\..\prev_cmp_CLOCK.qmsg
.....\..\prev_cmp_CLOCK.tan.qmsg
.....\jtag.log
    

CodeBus www.codebus.net