Description: The code is mainly to achieve the static SRAM control, is divided into three modules, control, data generating portion of the path, SRAM implementation of write and read operations.
To Search:
File list (Check if you may need any files):
sdram_control\doc\read_me.doc
.............\...\SDRAM.doc
.............\...\sdr_sdram.pdf
.............\sim\altera_mf.qpf
.............\...\altera_mf.qsf
.............\...\altera_mf.qws
.............\...\altera_mf.v
.............\...\Command.v
.............\...\control_interface.v
.............\...\db\altera_mf.db_info
.............\...\..\altera_mf.eco.cdb
.............\...\..\altera_mf.sld_design_entry.sci
.............\...\mt48lc2m32b2.v
.............\...\Params.v
.............\...\sdram_test.cr.mti
.............\...\sdram_test.mpf
.............\...\sdram_test.wlf
.............\...\sdram_test_tb.v
.............\...\transcript
.............\...\vsim.wlf
.............\...\wave.do
.............\...\.ork\@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s\verilog.asm
.............\...\....\..........................................\_primary.dat
.............\...\....\..........................................\_primary.vhd
.............\...\....\.m@f_pll_reg\verilog.asm
.............\...\....\............\_primary.dat
.............\...\....\............\_primary.vhd
.............\...\....\.....ram7x20_syn\verilog.asm
.............\...\....\................\_primary.dat
.............\...\....\................\_primary.vhd
.............\...\....\.....stratixii_pll\verilog.asm
.............\...\....\..................\_primary.dat
.............\...\....\..................\_primary.vhd
.............\...\....\............_pll\verilog.asm
.............\...\....\................\_primary.dat
.............\...\....\................\_primary.vhd
.............\...\....\alt3pram\verilog.asm
.............\...\....\........\_primary.dat
.............\...\....\........\_primary.vhd
.............\...\....\...accumulate\verilog.asm
.............\...\....\.............\_primary.dat
.............\...\....\.............\_primary.vhd
.............\...\....\...cam\verilog.asm
.............\...\....\......\_primary.dat
.............\...\....\......\_primary.vhd
.............\...\....\....dr_rx\verilog.asm
.............\...\....\.........\_primary.dat
.............\...\....\.........\_primary.vhd
.............\...\....\.......tx\verilog.asm
.............\...\....\.........\_primary.dat
.............\...\....\.........\_primary.vhd
.............\...\....\....lklock\verilog.asm
.............\...\....\..........\_primary.dat
.............\...\....\..........\_primary.vhd
.............\...\....\...ddio_bidir\verilog.asm
.............\...\....\.............\_primary.dat
.............\...\....\.............\_primary.vhd
.............\...\....\........in\verilog.asm
.............\...\....\..........\_primary.dat
.............\...\....\..........\_primary.vhd
.............\...\....\........out\verilog.asm
.............\...\....\...........\_primary.dat
.............\...\....\...........\_primary.vhd
.............\...\....\....pram\verilog.asm
.............\...\....\........\_primary.dat
.............\...\....\........\_primary.vhd
.............\...\....\...fp_mult\verilog.asm
.............\...\....\..........\_primary.dat
.............\...\....\..........\_primary.vhd
.............\...\....\...lvds_rx\verilog.asm
.............\...\....\..........\_primary.dat
.............\...\....\..........\_primary.vhd
.............\...\....\........tx\verilog.asm
.............\...\....\..........\_primary.dat
.............\...\....\..........\_primary.vhd
.............\...\....\...mult_accum\verilog.asm
.............\...\....\.............\_primary.dat
.............\...\....\.............\_primary.vhd
.............\...\....\.........dd\verilog.asm
.............\...\....\...........\_primary.dat
.............\...\....\...........\_primary.vhd
.............\...\....\...pll\verilog.asm
.............\...\....\......\_primary.dat
.............\...\....\......\_primary.vhd
.............\...\....\...qpram\verilog.asm
.............\...\....\........\_primary.dat
.............\...\....\........\_primary.vhd
.............\...\....\...shift_taps\verilog.asm
.............\...\....\.............\_primary.dat
.............\...\....\.............\_primary.vhd
.............\...\....\....qrt
Download