- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 1kb
- Update:
- 2012-11-26
- Downloads:
- 0 Times
- Uploaded by:
- 小姚
Description: Divider: the use of the count clock frequency into 10M 25M points, and in the development of on-board LED to achieve the Marquee.
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FPGA_TOP_ForYaoQi.vhd
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