- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 1kb
- Update:
- 2012-11-26
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- 0 Times
- Uploaded by:
- 陈诚
Description: The use of VHDL language the MAX7317' s acquisition program, this sub-module is loaded into the main program.
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