Pipeline-and-FIFO Pipeline and FIFO FPGA design

Title: Pipeline-and-FIFO

Category:
VHDL-FPGA-Verilog
Tags:
[VHDL] [源码]
File Size:
9kb
Update:
2012-12-02
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Uploaded by:
sun

Description: Pipeline and FIFO FPGA design

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Pipeline and FIFO\Circular_Buffer_1.v
.................\Circular_Buffer_2.v
.................\FIFO_Buffer.v
.................\Ser_Par_Conv_32.v
.................\Ser_Par_Conv_8.v
.................\t_Circular_Buffers.v
.................\t_FIFO_Buffer.v
.................\t_FIFO_Clock_Domain_Synch.v
.................\t_Ser_Par_Conv_32.v
.................\t_Ser_Par_Conv_8.v
.................\t_write_synch.v
.................\write_synch.v
.................\_vti_cnf\Circular_Buffer_1.v
.................\........\Circular_Buffer_2.v
.................\........\FIFO_Buffer.v
.................\........\Ser_Par_Conv_32.v
.................\........\Ser_Par_Conv_8.v
.................\........\t_Circular_Buffers.v
.................\........\t_FIFO_Buffer.v
.................\........\t_FIFO_Clock_Domain_Synch.v
.................\........\t_Ser_Par_Conv_32.v
.................\........\t_Ser_Par_Conv_8.v
.................\........\t_write_synch.v
.................\........\write_synch.v
.................\_vti_cnf
Pipeline and FIFO

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