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Title: zynq_base_trd_14_3 Download
 Description: Video Targeted Reference Design On Xilinx FPGA With Verilog
 Downloaders recently: [More information of uploader xushuang]
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zynq_base_trd_14_3
..................\boot_image
..................\..........\system.bit
..................\..........\u-boot.elf
..................\..........\zynq_fsbl.elf
..................\doc
..................\...\LICENSE.GPL3
..................\...\README.txt
..................\hw
..................\..\pa_proj
..................\..\.......\zynq_base_trd.data
..................\..\.......\..................\constrs_1
..................\..\.......\..................\.........\fileset.xml
..................\..\.......\..................\runs
..................\..\.......\..................\....\impl_1.psg
..................\..\.......\..................\....\runs.xml
..................\..\.......\..................\....\synth_1.psg
..................\..\.......\..................\sources_1
..................\..\.......\..................\.........\fileset.xml
..................\..\.......\zynq_base_trd.ppr
..................\..\.......\zynq_base_trd.srcs
..................\..\.......\..................\constrs_1
..................\..\.......\..................\.........\system_stub.ucf
..................\..\.......\..................\sources_1
..................\..\.......\..................\.........\edk
..................\..\.......\..................\.........\...\xps_proj
..................\..\.......\..................\.........\...\........\data
..................\..\.......\..................\.........\...\........\....\ps7_system_prj.xml
..................\..\.......\..................\.........\...\........\pcores
..................\..\.......\..................\.........\...\........\......\axi_tpg_v2_00_c
..................\..\.......\..................\.........\...\........\......\...............\data
..................\..\.......\..................\.........\...\........\......\...............\....\axi_tpg_v2_1_0.mpd
..................\..\.......\..................\.........\...\........\......\...............\....\axi_tpg_v2_1_0.pao
..................\..\.......\..................\.........\...\........\......\...............\hdl
..................\..\.......\..................\.........\...\........\......\...............\...\vhdl
..................\..\.......\..................\.........\...\........\......\...............\...\....\AWGN.vhd
..................\..\.......\..................\.........\...\........\......\...............\...\....\axi_tpg.vhd
..................\..\.......\..................\.........\...\........\......\...............\...\....\tpg_core.vhd
..................\..\.......\..................\.........\...\........\......\...............\...\....\user_logic.vhd
..................\..\.......\..................\.........\...\........\......\...............\...\....\zplate_pkg.vhd
..................\..\.......\..................\.........\...\........\......\...............\...\....\zplate_top.vhd
..................\..\.......\..................\.........\...\........\......\clk_detect_v1_00_a
..................\..\.......\..................\.........\...\........\......\..................\data
..................\..\.......\..................\.........\...\........\......\..................\....\clk_detect_v2_1_0.mpd
..................\..\.......\..................\.........\...\........\......\..................\....\clk_detect_v2_1_0.pao
..................\..\.......\..................\.........\...\........\......\..................\hdl
..................\..\.......\..................\.........\...\........\......\..................\...\vhdl
..................\..\.......\..................\.........\...\........\......\..................\...\....\clk_detect.vhd
..................\..\.......\..................\.........\...\........\......\..................\...\....\user_logic.vhd
..................\..\.......\..................\.........\...\........\......\fmc_imageon_hdmi_in_v1_03_a
..................\..\.......\..................\.........\...\........\......\...........................\data
..................\..\.......\..................\.........\...\........\....

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