- Category:
- Project Design
- Tags:
-
- File Size:
- 17kb
- Update:
- 2012-12-14
- Downloads:
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- Uploaded by:
- ali
Description: To design fixed point to floating point encoder and experiment with
simulation, synthesis and implementation features of the Xilinx Project navigator.
Specifically, the objectives of this lab are:
1. To try out basic building blocks of VHDL behavioral description especially
processes.
2. To learn how to translate problem specification into VHDL code.
3. To consolidate understanding of the development board and to learn different
techniques of utilizing its resources.
4. To consolidate test bench writing skills.
To Search:
File list (Check if you may need any files):
FPGA_Project\cg.vhd
............\counter.vhd
............\font_unit.vhd
............\s.vhd
............\text.vhd
............\top.ucf
............\top.vhd
............\vga.vhd
............\vga_counter.bit
FPGA_Project
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