- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 1kb
- Update:
- 2012-12-14
- Downloads:
- 0 Times
- Uploaded by:
- 君君
Description: 50MHz clock signal at a frequency of 1Hz, to count the 1 Hz square wave signal, and using 4 Siamese digital tube dynamic display
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