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VHDL-FPGA-Verilog
Title:
counter60
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Category:
VHDL-FPGA-Verilog
Tags:
[WORD]
File Size:
283kb
Update:
2012-12-15
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0 Times
Uploaded by:
veryshi
Description:
Experimental plate to achieve mode 60 counts, namely 00-01-02-03-04- ... 59-00-01 ... AN1 ~ AN0 Basys2 experiment board with (LD7 ~ LD0).
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counter60.doc
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