- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 59kb
- Update:
- 2012-12-18
- Downloads:
- 0 Times
- Uploaded by:
- 沈微
Description: Simple signal generator can output three waveforms, incremental sawtooth generator module, the sine wave generator module, a square wave generator module, waveform selector module, vhdl
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xinhao\Block1.bdf
......\db\sin.cbx.xml
......\..\sin.cmp.rdb
......\..\sin.dbp
......\..\sin.db_info
......\..\sin.eco.cdb
......\..\sin.hier_info
......\..\sin.hif
......\..\sin.map.cdb
......\..\sin.map.hdb
......\..\sin.map.logdb
......\..\sin.map.qmsg
......\..\sin.pre_map.cdb
......\..\sin.pre_map.hdb
......\..\sin.psp
......\..\sin.rtlv.hdb
......\..\sin.rtlv_sg.cdb
......\..\sin.rtlv_sg_swap.cdb
......\..\sin.sgdiff.cdb
......\..\sin.sgdiff.hdb
......\..\sin.sld_design_entry.sci
......\..\sin.sld_design_entry_dsc.sci
......\..\sin.syn_hier_info
......\signal_select.bsf
......\signal_select.vhd
......\sin.bsf
......\sin.done
......\sin.flow.rpt
......\sin.map.rpt
......\sin.map.summary
......\sin.qpf
......\sin.qsf
......\sin.qws
......\sin.vhd
......\up_zigzag.bsf
......\up_zigzag.vhd
......\xwhappy.bsf
......\xwhappy.vhd
......\db
xinhao
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