DDR SDRAM控制器verilog代码及中文说明文档
........................................\DDR SDRAM控制器源代码
........................................\.....................\mem_interface_top.v
........................................\.....................\mem_interface_top_RAM_D_0.v
........................................\.....................\mem_interface_top_addr_gen_0.v
........................................\.....................\mem_interface_top_backend_fifos_0.v
........................................\.....................\mem_interface_top_backend_rom_0.v
........................................\.....................\mem_interface_top_cmp_rd_data_0.v
........................................\.....................\mem_interface_top_controller_iobs_0.v
........................................\.....................\mem_interface_top_data_gen_16.v
........................................\.....................\mem_interface_top_data_path_0.v
........................................\.....................\mem_interface_top_data_path_iobs_0.v
........................................\.....................\mem_interface_top_data_tap_inc.v
........................................\.....................\mem_interface_top_data_write_0.v
........................................\.....................\mem_interface_top_ddr_controller_0.v
........................................\.....................\mem_interface_top_idelay_ctrl.v
........................................\.....................\mem_interface_top_infrastructure.v
........................................\.....................\mem_interface_top_infrastructure_iobs_0.v
........................................\.....................\mem_interface_top_iobs_0.v
........................................\.....................\mem_interface_top_main_0.v
........................................\.....................\mem_interface_top_parameters_0.v
........................................\.....................\mem_interface_top_pattern_compare8.v
........................................\.....................\mem_interface_top_rd_data_0.v
........................................\.....................\mem_interface_top_rd_data_fifo_0.v
........................................\.....................\mem_interface_top_rd_wr_addr_fifo_0.v
........................................\.....................\mem_interface_top_tap_ctrl_0.v
........................................\.....................\mem_interface_top_tap_logic_0.v
........................................\.....................\mem_interface_top_test_bench_0.v
........................................\.....................\mem_interface_top_top_0.v
........................................\.....................\mem_interface_top_user_interface_0.v
........................................\.....................\mem_interface_top_v4_dm_iob.v
........................................\.....................\mem_interface_top_v4_dq_iob.v
........................................\.....................\mem_interface_top_v4_dqs_iob.v
........................................\.....................\mem_interface_top_wr_data_fifo_16.v
........................................\使用 Virtex-4 FPGA 器件实现DDR SDRAM控制器.pdf