Description: DDS signal generator can generate a square wave, and some small modifications to the next input data to generate arbitrary waveforms.
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File list (Check if you may need any files):
DDC_VHDL\adder10b.vhd
........\adder10b.vhd.bak
........\adder32b.vhd
........\db\add_sub_1ph.tdf
........\..\add_sub_4rh.tdf
........\..\add_sub_5rh.tdf
........\..\add_sub_8rh.tdf
........\..\add_sub_knh.tdf
........\..\add_sub_toh.tdf
........\..\altsyncram_2to3.tdf
........\..\altsyncram_6to3.tdf
........\..\altsyncram_io51.tdf
........\..\altsyncram_v672.tdf
........\..\cntr_cmi.tdf
........\..\cntr_o3i.tdf
........\..\cntr_p3i.tdf
........\..\cntr_rpi.tdf
........\..\cntr_spi.tdf
........\..\cntr_t3i.tdf
........\..\DDC_VHDL.db_info
........\..\DDC_VHDL.eco.cdb
........\..\DDC_VHDL.sim_ori.vwf
........\..\DDC_VHDL.sld_design_entry.sci
........\..\decode_9jf.tdf
........\..\decode_ogi.tdf
........\..\mux_cfc.tdf
........\..\mux_ogc.tdf
........\..\mux_oic.tdf
........\..\mux_sgc.tdf
........\..\prev_cmp_DDC_VHDL.asm.qmsg
........\..\prev_cmp_DDC_VHDL.fit.qmsg
........\..\prev_cmp_DDC_VHDL.map.qmsg
........\..\prev_cmp_DDC_VHDL.qmsg
........\..\prev_cmp_DDC_VHDL.sim.qmsg
........\..\prev_cmp_DDC_VHDL.tan.qmsg
........\..\wed.wsf
........\DDC_VHDL.asm.rpt
........\DDC_VHDL.cdf
........\DDC_VHDL.done
........\DDC_VHDL.dpf
........\DDC_VHDL.fit.rpt
........\DDC_VHDL.fit.smsg
........\DDC_VHDL.fit.summary
........\DDC_VHDL.flow.rpt
........\DDC_VHDL.jdi
........\DDC_VHDL.map.rpt
........\DDC_VHDL.map.summary
........\DDC_VHDL.MOD
........\DDC_VHDL.pin
........\DDC_VHDL.pof
........\DDC_VHDL.qpf
........\DDC_VHDL.qsf
........\DDC_VHDL.qws
........\DDC_VHDL.sim.rpt
........\DDC_VHDL.sof
........\DDC_VHDL.tan.rpt
........\DDC_VHDL.tan.summary
........\DDC_VHDL.vhd
........\DDC_VHDL.vhd.bak
........\DDC_VHDL.vwf
........\DDC_VHDL1.MOD
........\DDC_VHDL_assignment_defaults.qdf
........\reg10b.vhd
........\reg10b.vhd.bak
........\reg32b.vhd
........\sin\Debug\sin.exe
........\...\.....\sin.ilk
........\...\.....\sin.mif
........\...\.....\sin.mif.bak
........\...\.....\sin.obj
........\...\.....\sin.pch
........\...\.....\sin.pdb
........\...\.....\vc60.idb
........\...\.....\vc60.pdb
........\...\sin.c
........\...\sin.dsp
........\...\sin.dsw
........\...\sin.ncb
........\...\sin.opt
........\...\sin.plg
........\sin.vhd
........\sin.vhd.bak
........\stp1.stp
........\.in\Debug
........\db
........\sin
DDC_VHDL
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