- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 214kb
- Update:
- 2012-11-26
- Downloads:
- 0 Times
- Uploaded by:
- 张鹏
Description: ddr2 controller code (package includes the memory of the simulation model) leon3 system, the controller can with amba2.0 the ahb bus connected to more complex institutions, the amount of code
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毕业设计源代码\allddr.vhd
..............\allmem.vhd
..............\allpads.vhd
..............\amba.vhd
..............\config.vhd
..............\DataSender.vhd
..............\ddr2buf.vhd
..............\ddr2related.vhd
..............\ddr2spa.vhd
..............\ddr2spax.vhd
..............\ddr2spax_ahb.vhd
..............\ddr2spax_ddr.vhd
..............\ddrphy.vhd
..............\ddrphy_wrap.vhd
..............\ddr_phy_inferred.vhd
..............\ddr_phy_unisim.vhd
..............\ddr_unisim.vhd
..............\delay_wire.vhd
..............\devices.vhd
..............\gencomp.vhd
..............\HY5PS121621F.vhd
..............\HY5PS121621F_PACK.vhd
..............\iodpad.vhd
..............\iopad.vhd
..............\iopad_ds.vhd
..............\memctrl.vhd
..............\memory_inferred.vhd
..............\outpad.vhd
..............\pas_unisim.vhd
..............\sim.vhd
..............\simple_simprim.vhd
..............\stdio.vhd
..............\stdlib.vhd
..............\syncram_2p.vhd
..............\test_bench.vhd
..............\unisim_VCOMP.vhd
..............\unisim_VITAL.vhd
..............\unisim_VPKG.vhd
毕业设计源代码
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