Day1\edk\Digilent\boards\Digilent_Atlys\data\bitgen.ut_quad_spi
....\...\........\......\..............\....\BSB_Component.xml
....\...\........\......\..............\....\Digilent_Atlys.mpd
....\...\........\......\..............\....\Digilent_Atlys.tcl
....\...\........\......\..............\....\Digilent_Atlys.xml
....\...\........\......\..............\....\Digilent_Atlys_pins.csv
....\...\........\......\..............\....\Digilent_Atlys_v2_2_0.xbd
....\...\........\......\..............\....\download.cmd
....\...\........\......\..............\....\README.txt
....\...\........\......\..............\....\Soft_TEMAC_axi_ethernet_v1_00_a.ucf
....\...\........\......\..............\....\Soft_TEMAC_xps_ll_temac.ucf
....\...\........\ipxact\Digilent_Atlys\data\BSB_Component.xml
....\...\........\......\..............\....\Digilent_Atlys.tcl
....\...\........\......\..............\....\Digilent_Atlys.xml
....\...\........\......\..............\....\Digilent_Atlys_pins.csv
....\...\........\......\..............\....\download.cmd
....\...\........\......\..............\....\Soft_TEMAC_axi_ethernet_v1_00_a.ucf
....\...\Digilent.zip
....\...\edk101.pdf
....\...\lab1\bitfiles\download.bit
....\...\....\........\memory_tests_0.elf
....\...\....\........\system.bit
....\...\....\........\system_bd.bmm
....\...\....\.lockdiagram\system.jpg
....\...\....\............\system.svg
....\...\....\clock_generator_0.log
....\...\....\data\system.ucf
....\...\....\etc\bitgen.ut
....\...\....\...\download.cmd
....\...\....\...\fast_runtime.opt
....\...\....\...\system.filters
....\...\....\...\system.gui
....\...\....\hdl\axi4lite_0_wrapper.v
....\...\....\...\axi4_0_wrapper.v
....\...\....\...\clock_generator_0_wrapper.vhd
....\...\....\...\debug_module_wrapper.vhd
....\...\....\...\elaborate\clock_generator_0_v4_01_a\hdl\vhdl\clock_generator.vhd
....\...\....\...\.........\microblaze_0_bram_block_elaborate_v1_00_a\hdl\vhdl\microblaze_0_bram_block_elaborate.vhd
....\...\....\...\mcb_ddr2_wrapper.v
....\...\....\...\microblaze_0_bram_block_wrapper.vhd
....\...\....\...\microblaze_0_dlmb_wrapper.vhd
....\...\....\...\microblaze_0_d_bram_ctrl_wrapper.vhd
....\...\....\...\microblaze_0_ilmb_wrapper.vhd
....\...\....\...\microblaze_0_i_bram_ctrl_wrapper.vhd
....\...\....\...\microblaze_0_wrapper.vhd
....\...\....\...\proc_sys_reset_0_wrapper.vhd
....\...\....\...\rs232_uart_1_wrapper.vhd
....\...\....\...\system.vhd
....\...\....\...\system_stub.vhd
....\...\....\platgen.log
....\...\....\platgen.opt
....\...\....\psf2Edward.log
....\...\....\SDK\SDK_Export\hw\docs\ip\axi_interconnect.pdf
....\...\....\...\..........\..\....\..\axi_s6_ddrx.pdf
....\...\....\...\..........\..\....\..\axi_uartlite.pdf
....\...\....\...\..........\..\....\..\bram_block.pdf
....\...\....\...\..........\..\....\..\clock_generator.pdf
....\...\....\...\..........\..\....\..\lmb_bram_if_cntlr.pdf
....\...\....\...\..........\..\....\..\lmb_v10.pdf
....\...\....\...\..........\..\....\..\mdm.pdf
....\...\....\...\..........\..\....\..\microblaze.pdf
....\...\....\...\..........\..\....\..\proc_sys_reset.pdf
....\...\....\...\..........\..\imgs\axi4lite_0.jpg
....\...\....\...\..........\..\....\axi4lite_0.svg
....\...\....\...\..........\..\....\axi4_0.jpg
....\...\....\...\..........\..\....\axi4_0.svg
....\...\....\...\..........\..\....\clock_generator_0.jpg
....\...\....\...\..........\..\....\clock_generator_0.svg
....\...\....\...\..........\..\....\debug_module.jpg
....\...\....\...\..........\..\....\debug_module.svg
....\...\....\...\..........\..\....\IMG_closeBranch.png
....\...\....\...\..........\..\....\IMG_LicensedCore.bmp
....\...\....\...\..........\..\....\IMG_openBranch.png
....\...\....\...\..........\..\....\MCB_DDR2.jpg
....\...\....\...\..........\..\....\MCB_DDR2.svg
....\...\....\...\..........\..\....\microblaze_0.jpg
....\...\....\...\..........\..\....\microblaze_0.svg
....\...\....\...\..........\..\....\microblaze_0_bram_block.jpg
....\...\....\...\..........\..\....\microblaze_0_bram_block.svg
....\...\....\...\..........\..\....\micro