Verilog\ascii_bcd.v
.......\bcd_ascii.v
.......\buzz.v
.......\clock.v
.......\counter.v
.......\counter_core.v
.......\counter_sim.v
.......\delay_time.v
.......\divisor.v
.......\div_sim.v
.......\div_sim.v.bak
.......\ds_drv.v
.......\ds_drv_s.bdf
.......\ds_drv_s.v
.......\ds_sel.v
.......\fifo.v
.......\flash.v
.......\i2c.v
.......\io_tri_state.v
.......\kb2bcd.v
.......\kb_drv.v
.......\kb_drv_test.v
.......\key.v
.......\lcd1602_drv.v
.......\led_drv.v
.......\mseq.v
.......\msg_decode.v
.......\msg_decode_test.v
.......\msg_encode.v
.......\mt48lc4m32b2.v
.......\mt48lc4m32b2_test.v
.......\ps2_drv.v
.......\pwm.v
.......\pwm_counter.v
.......\s373.v
.......\s373.v.bak
.......\scan_ascii.v
.......\sdram.v
.......\sdram.v.bak
.......\sel8.v
.......\shifter.v
.......\spi.v
.......\timer.v
.......\uart_rx.v
.......\uart_tx.v
.......\usb.v
.......\vga_drv.v
.......\复件 sdram.v
Verilog