Description: The source code is RS (31,19) code complete encoding and decoding procedures, and spend a lot of time using is VerilogHDL language contains the encoding and decoding of RS codes, this egg pain
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File list (Check if you may need any files):
RS2\RS\FF.v
...\..\GFADD.v
...\..\iseconfig\RS.projectmgr
...\..\.........\rs_encoder.xreport
...\..\lcpmult.v
...\..\modelsim.ini
...\..\RS.gise
...\..\RS.xise
...\..\rs_encoder.cmd_log
...\..\rs_encoder.lso
...\..\rs_encoder.ngc
...\..\rs_encoder.ngr
...\..\rs_encoder.prj
...\..\rs_encoder.stx
...\..\rs_encoder.syr
...\..\RS_ENCODER.V
...\..\RS_ENCODER.V.bak
...\..\rs_encoder.xst
...\..\rs_encoder_envsettings.html
...\..\rs_encoder_summary.html
...\..\rs_encoder_xst.xrpt
...\..\test_RS.fdo
...\..\test_RS.udo
...\..\test_RS.v
...\..\test_RS_wave.fdo
...\..\transcript
...\..\vsim.wlf
...\..\webtalk_pn.xml
...\..\.ork\@f@f\_primary.dat
...\..\....\....\_primary.dbs
...\..\....\....\_primary.vhd
...\..\....\.g@f@a@d@d\_primary.dat
...\..\....\..........\_primary.dbs
...\..\....\..........\_primary.vhd
...\..\....\._opt\vopt0f4sex
...\..\....\.....\vopt266kzi
...\..\....\.....\vopt47xjwv
...\..\....\.....\vopt4zsnex
...\..\....\.....\vopt5nvhzi
...\..\....\.....\vopt6rynxi
...\..\....\.....\vopt7ydgfx
...\..\....\.....\vopt8zaiyy
...\..\....\.....\vopt96hdzi
...\..\....\.....\vopt9qigyi
...\..\....\.....\vopta8kjxi
...\..\....\.....\voptan6axv
...\..\....\.....\voptbe3cfx
...\..\....\.....\voptbiyfxk
...\..\....\.....\voptd78dyi
...\..\....\.....\voptdr9fxi
...\..\....\.....\vopte6w7xv
...\..\....\.....\vopteyr9fx
...\..\....\.....\voptgqxayi
...\..\....\.....\vopth8zcxi
...\..\....\.....\voptiee6fx
...\..\....\.....\voptinh3xv
...\..\....\.....\voptizf9ex
...\..\....\.....\voptkqi6e8
...\..\....\.....\voptkrk9xi
...\..\....\.....\voptm670xv
...\..\....\.....\voptnf55ex
...\..\....\.....\voptny33fx
...\..\....\.....\voptqm5yzi
...\..\....\.....\voptr783e8
...\..\....\.....\voptr8a6xi
...\..\....\.....\voptseszex
...\..\....\.....\voptszt2ex
...\..\....\.....\voptt5vvzi
...\..\....\.....\voptwrz2xi
...\..\....\.....\voptxfgzdx
...\..\....\.....\voptxyewex
...\..\....\.....\voptymgqzi
...\..\....\.....\voptz8mzwi
...\..\....\.....\_deps
...\..\....\glbl\_primary.dat
...\..\....\....\_primary.dbs
...\..\....\....\_primary.vhd
...\..\....\lcpmult\_primary.dat
...\..\....\.......\_primary.dbs
...\..\....\.......\_primary.vhd
...\..\....\rs_encoder\_primary.dat
...\..\....\..........\_primary.dbs
...\..\....\..........\_primary.vhd
...\..\....\test_@r@s\_primary.dat
...\..\....\.........\_primary.dbs
...\..\....\.........\_primary.vhd
...\..\....\_info
...\..\....\.temp\vlog4yekri
...\..\....\.....\vlogk95b1t
...\..\....\_vmake
...\..\xst\work\hdllib.ref
...\..\...\....\vlg24\_f_f.bin
...\..\...\....\....8\rs__encoder.bin
...\..\...\....\...71\lcpmult.bin
...\..\...\....\....6\_g_f_a_d_d.bin
...\..\_xmsgs\pn_parser.xmsgs
...\..\......\xst.xmsgs
...\sim.do
...\vsim.wlf
...\work\@f@f\verilog.asm
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