Description: the sip interface master controller code and code from the controller, use register-based the SPPI interface of communication, including simulation, synthesis results
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File list (Check if you may need any files):
ssimple_spi_li\simple_spi\tags\initial\rtl\verilog\fifo4.v
..............\..........\....\.......\...\.......\simple_spi_top.v
..............\..........\.runk\bench\verilog\spi_slave_model.v
..............\..........\.....\.....\.......\tst_bench_top.v
..............\..........\.....\.....\.......\wb_master_model.v
..............\..........\.....\doc\simple_spi.pdf
..............\..........\.....\...\.rc\simple_spi.doc
..............\..........\.....\rtl\verilog\fifo4.v
..............\..........\.....\...\.......\simple_spi_top.v
..............\..........\.....\sim\rtl_sim\bin\Makefile
..............\..........\.....\...\.......\run\Makefile
..............\..........\.....\...\.......\...\ncsim.log
..............\..........\.....\...\.......\...\ncvlog.log
..............\..........\.....\...\.......\...\..work\cds.lib
..............\..........\.....\...\.......\...\......\hdl.var
..............\..........\.....\...\.......\...\......\work\.cdsvmod
..............\..........\.....\...\.......\...\......\....\.inca.db.135.linux
..............\..........\.....\...\.......\...\......\....\.inca.db.148.lnx86
..............\..........\.....\...\.......\...\......\....\inca.linux.135.pak
..............\..........\.....\...\.......\...\......\....\inca.lnx86.148.pak
..............\..........\.....\...\.......\...\simvision.sv
..............\..........\.....\...\.......\...\stdout.log
..............\..........\.....\...\.......\...\waves\waves.do
..............\..........\.....\...\.......\...\ncwork\work
..............\..........\.....\...\.......\...\ncwork
..............\..........\.....\...\.......\...\waves
..............\..........\.ags\initial\rtl\verilog
..............\..........\.runk\sim\rtl_sim\bin
..............\..........\.....\...\.......\run
..............\..........\.ags\initial\rtl
..............\..........\.runk\bench\verilog
..............\..........\.....\doc\src
..............\..........\.....\rtl\verilog
..............\..........\.....\sim\rtl_sim
..............\..........\.ags\initial
..............\..........\.runk\bench
..............\..........\.....\doc
..............\..........\.....\rtl
..............\..........\.....\sim
..............\..........\branches
..............\..........\tags
..............\..........\trunk
..............\..........\web_uploads
..............\simple_spi
ssimple_spi_li
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