Description: 8b10b encoder design of high-speed data transmission encoding, including source code, there are specific design documents
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RD1012_rev01.2\docs
..............\....\rd1012.pdf
..............\....\rd1012_readme.txt
..............\project
..............\.......\4k
..............\.......\..\verilog
..............\.......\..\.......\8b_10b_enc_dec.lct
..............\.......\..\vhdl
..............\.......\..\....\8b_10b_enc_dec.lct
..............\.......\ecp_ec
..............\.......\......\verilog
..............\.......\......\.......\8b_10b_enc_dec.lpf
..............\.......\......\vhdl
..............\.......\......\....\8b_10b_enc_dec.lpf
..............\.......\ecp2m
..............\.......\.....\verilog
..............\.......\.....\.......\enc_dec.lpf
..............\.......\.....\.......\Strategy1.sty
..............\.......\.....\vhdl
..............\.......\.....\....\enc_dec.lpf
..............\.......\.....\....\Strategy1.sty
..............\.......\ecp3
..............\.......\....\verilog
..............\.......\....\.......\enc_dec.lpf
..............\.......\....\.......\Strategy1.sty
..............\.......\....\vhdl
..............\.......\....\....\enc_dec.lpf
..............\.......\....\....\Strategy1.sty
..............\.......\xo
..............\.......\..\verilog
..............\.......\..\.......\8b_10b_enc_dec.lpf
..............\.......\..\vhdl
..............\.......\..\....\8b_10b_enc_dec.lpf
..............\.......\xo2
..............\.......\...\verilog
..............\.......\...\.......\enc_dec.lpf
..............\.......\...\.......\Strategy1.sty
..............\.......\...\vhdl
..............\.......\...\....\enc_dec.lpf
..............\.......\...\....\Strategy1.sty
..............\.......\xp2
..............\.......\...\verilog
..............\.......\...\.......\enc_dec.lpf
..............\.......\...\.......\Strategy1.sty
..............\.......\...\vhdl
..............\.......\...\....\enc_dec.lpf
..............\.......\...\....\Strategy1.sty
..............\simulation
..............\..........\4k
..............\..........\..\verilog
..............\..........\..\.......\tb_top_net_8b10b_tfa.udo
..............\..........\..\.......\tb_top_net_8b10b_tffa.udo
..............\..........\..\vhdl
..............\..........\..\....\tb_top_net_8b10b_vhda.udo
..............\..........\..\....\tb_top_net_8b10b_vhdaf.udo
..............\..........\ecp_ec
..............\..........\......\verilog
..............\..........\......\.......\tb_top_net_8b10b_tf.udo
..............\..........\......\.......\tb_top_net_8b10b_tff.udo
..............\..........\......\vhdl
..............\..........\......\....\tb_top_net_8b10b_vhd.udo
..............\..........\......\....\tb_top_net_8b10b_vhdf.udo
..............\..........\ecp2m
..............\..........\.....\verilog
..............\..........\.....\.......\enc_dec_enc_dec_vo.sdf
..............\..........\.....\.......\enc_dec_enc_dec_vo.vo
..............\..........\.....\.......\rtlsim.do
..............\..........\.....\.......\timesim.do
..............\..........\.....\vhdl
..............\..........\.....\....\enc_dec_enc_dec_vho.sdf
..............\..........\.....\....\enc_dec_enc_dec_vho.vho
..............\..........\.....\....\rtlsim.do
..............\..........\.....\....\timesim.do
..............\..........\ecp3
..............\..........\....\verilog
..............\..........\....\.......\enc_dec_enc_dec_vo.sdf
..............\..........\....\.......\enc_dec_enc_dec_vo.vo
..............\..........\....\.......\rtlsim.do
..............\..........\....\.......\timesim.do
..............\..........\....\vhdl
..............\..........\....\....\enc_dec_enc_dec_vho.sdf
..............\..........\....\....\enc_dec_enc_dec_vho.vho
..............\..........\....\....\rtlsim.do
..............\..........\....\....\timesim.do
..............\..........\xo
..............\..........\..\verilog
..............\..........\..\.......\tb_top_net_8b10b_tf.udo
..............\..........\..\.......\tb_top_net_8b10b_tff.udo
..............\..........\..\vhdl
..............\..........\..\....\tb_top_net_8b10b_vhd.udo
..............\..........\..\....\tb_top_net_8b10b_vhdf.udo
..............\..........\xo2
..............\..........\...\
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