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Title: Lab_COUNTER Download
  • Category:
  • VHDL-FPGA-Verilog
  • Tags:
  • File Size:
  • 2kb
  • Update:
  • 2012-11-26
  • Downloads:
  • 0 Times
  • Uploaded by:
  • fox
 Description: Lab experiment : 50 MHz clk 4 bit counter (CLR + parallel load + pause ) on spartan3e
 Downloaders recently: [More information of uploader fox]
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counter_tb.vhd
counter.ucf
counter.vhd

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