Description: The verilog code describes a simple, single-cycle MIPS processor implementation, and debugging through in ModelSim SE6.5c,.
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File list (Check if you may need any files):
SCMIPS
......\memfile.dat
......\SCMIPS.cr.mti
......\SCMIPS.mpf
......\SCMIPS.v
......\SCMIPS.v.bak
......\testdata
......\........\memfile.dat
......\........\mipstest.asm
......\vsim.wlf
......\work
......\....\adder
......\....\.....\verilog.asm
......\....\.....\verilog.rw
......\....\.....\_primary.dat
......\....\.....\_primary.dbs
......\....\.....\_primary.vhd
......\....\alu
......\....\aludec
......\....\......\verilog.asm
......\....\......\verilog.rw
......\....\......\_primary.dat
......\....\......\_primary.dbs
......\....\......\_primary.vhd
......\....\...\verilog.asm
......\....\...\verilog.rw
......\....\...\_primary.dat
......\....\...\_primary.dbs
......\....\...\_primary.vhd
......\....\controller
......\....\..........\verilog.asm
......\....\..........\verilog.rw
......\....\..........\_primary.dat
......\....\..........\_primary.dbs
......\....\..........\_primary.vhd
......\....\datapath
......\....\........\verilog.asm
......\....\........\verilog.rw
......\....\........\_primary.dat
......\....\........\_primary.dbs
......\....\........\_primary.vhd
......\....\dmem
......\....\....\verilog.asm
......\....\....\verilog.rw
......\....\....\_primary.dat
......\....\....\_primary.dbs
......\....\....\_primary.vhd
......\....\flopr
......\....\.....\verilog.asm
......\....\.....\verilog.rw
......\....\.....\_primary.dat
......\....\.....\_primary.dbs
......\....\.....\_primary.vhd
......\....\imem
......\....\....\verilog.asm
......\....\....\verilog.rw
......\....\....\_primary.dat
......\....\....\_primary.dbs
......\....\....\_primary.vhd
......\....\maindec
......\....\.......\verilog.asm
......\....\.......\verilog.rw
......\....\.......\_primary.dat
......\....\.......\_primary.dbs
......\....\.......\_primary.vhd
......\....\mips
......\....\....\verilog.asm
......\....\....\verilog.rw
......\....\....\_primary.dat
......\....\....\_primary.dbs
......\....\....\_primary.vhd
......\....\mux2
......\....\....\verilog.asm
......\....\....\verilog.rw
......\....\....\_primary.dat
......\....\....\_primary.dbs
......\....\....\_primary.vhd
......\....\regfile
......\....\.......\verilog.asm
......\....\.......\verilog.rw
......\....\.......\_primary.dat
......\....\.......\_primary.dbs
......\....\.......\_primary.vhd
......\....\signext
......\....\.......\verilog.asm
......\....\.......\verilog.rw
......\....\.......\_primary.dat
......\....\.......\_primary.dbs
......\....\.......\_primary.vhd
......\....\sl2
......\....\...\verilog.asm
......\....\...\verilog.rw
......\....\...\_primary.dat
......\....\...\_primary.dbs
......\....\...\_primary.vhd
......\....\testbench
......\....\.........\verilog.asm
......\....\.........\verilog.rw
......\....\.........\_primary.dat
......\....\.........\_primary.dbs
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