- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 1kb
- Update:
- 2012-11-26
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- Uploaded by:
- 吴凤妹
Description: 1, Use 16:00 of 16* giving out light of the diode gradually go scanning to show " a" words. 2, The importation is four binary system vectors. 3, Adopt the method of row or column scanning, go to choose signal (altogether 16 rows) with four binary systems, if pick out the first, then the scanning first in which go is Gao Dian Ping (1), which go is low to give or get an electric shock even (0) Evenly then ordering for Gao Dian is bright, being low the electricity isn' t evenly bright. 4, Notice the constitution of scanning the frequency, scan frequency enough quickly, just can the dynamic state scan " a" words. 5, Procedure from go to scan a mold piece and show mold piece composing. The going to scan a mold piece an importation is a clock signal and resets signal, output to 4 binary systems (mean with the sel) to go to choose signal, use to pick out a line, carry on a scanning. Show a mold piece: In order to go to choose signal, the importation outputs to 16 binary
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