Description: This application note describes the design of a FPGA SDRAM controller.The controller has a system interface on one side and a SDRAM controller for two 16 MB SDRAMs on the other side.It can be easily modified to fit different memory
organizations of system speed and bandwidth requirements
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File list (Check if you may need any files):
sdram_controller\verilog\func_sim\func_sim.cfg
................\.......\........\func_sim.log
................\.......\........\func_sim.vpd
................\.......\........\run_sim
................\.......\........\string_decode_fn.v
................\.......\........\tb_sdrm.v
................\.......\micron\bank0.txt
................\.......\......\bank1.txt
................\.......\......\mt48lc1m16a1-8a.v
................\.......\......\mt48lc1m16a1-8a.v.bak
................\.......\......\mt48lc1m16a1.v
................\.......\......\test.v
................\.......\par\run_par
................\.......\...\sdrm.edf
................\.......\...\sdrm.ucf
................\.......\...\sdrm_par.sdf
................\.......\...\sdrm_par.v
................\.......\.ost_route\post_route.cfg
................\.......\..........\post_route.log
................\.......\..........\post_route.vpd
................\.......\..........\run_sim
................\.......\..........\sdrm_par.sdf
................\.......\..........\sdrm_par.v
................\.......\..........\string_decode_post_route.v
................\.......\..........\tb_post_route.v
................\.......\README
................\.......\src\brst_cntr.v
................\.......\...\cslt_cntr.v
................\.......\...\define.v
................\.......\...\ki_cntr.v
................\.......\...\rcd_cntr.v
................\.......\...\ref_cntr.v
................\.......\...\sdrm.v
................\.......\...\sdrmc_state.v
................\.......\...\sdrm_t.v
................\.......\...\sys_int.v
................\.......\...\transcript
................\.......\.ynth\run_synth
................\.......\.....\sdrm.edf
................\.......\.....\sdrm.scr
................\.......\.....\setup.scr
................\.......\func_sim
................\.......\micron
................\.......\par
................\.......\post_route
................\.......\src
................\.......\synth
................\verilog
sdram_controller
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