- Category:
- VHDL-FPGA-Verilog
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- File Size:
- 55kb
- Update:
- 2012-11-26
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- Uploaded by:
- 张永满
Description: 48M clock signal divider 1Khz signal by the output of the dig (2:0). Because the test board seven segment decoder monitors are common the same data line, must be provided to a fast scan signal (due to the stay of the human visual scanning signal must be greater than 20Hz, the system design is used 1Khz) by scanning player number and answer in the countdown and answer countdown display timeshare displayed on the seven-segment decoder displays with this system dig (2:0) three by 3_8 decoder timeshare elect three seven segment decoder monitor.
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5基于FPGA的扫描器设计和仿真.docx
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