Title:
2-to-4-Decoder-with--Configuration
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Description: 2-to-4 Decoder with Testbench and Configuration
This set of design units illustrates several features of the VHDL language including:
Using generics to pass time delay values to design entities.
Design hierarchy using instantiated components.
Test benches for design verification.
Configuration declaration for binding components to design entities and setting delay values.
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File list (Check if you may need any files):
2-to-4 Decoder with Testbench and Configuration.txt
