- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 80kb
- Update:
- 2012-11-26
- Downloads:
- 0 Times
- Uploaded by:
- 跳跳鱼
Description: The the experimental box standard AD_DA panel D/A converters, a round analog waveform, learning LPM_ROM (1024* 10) the megafunctions the customization and use last Quartus II to complete the design, simulation.
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File list (Check if you may need any files):
round\calculator.bsf
.....\calculator.vhd
.....\calculator.vhd.bak
.....\counter.asm.rpt
.....\counter.bsf
.....\counter.cdf
.....\counter.done
.....\counter.dpf
.....\counter.fit.rpt
.....\counter.fit.smsg
.....\counter.fit.summary
.....\counter.flow.rpt
.....\counter.map.rpt
.....\counter.map.summary
.....\counter.merge.rpt
.....\counter.pin
.....\counter.pof
.....\counter.qpf
.....\counter.qsf
.....\counter.qws
.....\counter.sim.rpt
.....\counter.sof
.....\counter.tan.rpt
.....\counter.tan.summary
.....\counter.vhd
.....\counter.vwf
.....\counter_assignment_defaults.qdf
.....\datarom.mif
.....\.b\add_sub_4rh.tdf
.....\..\add_sub_hsh.tdf
.....\..\altsyncram_rt21.tdf
.....\..\altsyncram_st21.tdf
.....\..\counter.db_info
.....\..\counter.eco.cdb
.....\..\counter.sim.cvwf
.....\..\counter.sim_ori.vwf
.....\..\counter.sld_design_entry.sci
.....\..\wed.wsf
.....\lpm_rom0.bsf
.....\lpm_rom0.cmp
.....\lpm_rom0.vhd
.....\ROM.bdf
.....\db
round
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