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Title: LAB-2 Download
 Description: With FPGA VGA control is not used niosII, just verilog hardware description language. The entire project.
 Downloaders recently: [More information of uploader 李娟]
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LAB 2\colormap.v
.....\db\altsyncram_0eq1.tdf
.....\..\altsyncram_7ri2.tdf
.....\..\altsyncram_i1l1.tdf
.....\..\altsyncram_k4p3.tdf
.....\..\cmpr_5vh.tdf
.....\..\cntr_2ci.tdf
.....\..\cntr_3sf.tdf
.....\..\cntr_4jg.tdf
.....\..\cntr_4qh.tdf
.....\..\cntr_cai.tdf
.....\..\cntr_dne.tdf
.....\..\cntr_gui.tdf
.....\..\cntr_p6j.tdf
.....\..\cntr_qjf.tdf
.....\..\decode_4oa.tdf
.....\..\decode_aoi.tdf
.....\..\decode_rqf.tdf
.....\..\design.amm.cdb
.....\..\design.asm.qmsg
.....\..\design.asm.rdb
.....\..\design.asm_labs.ddb
.....\..\design.cbx.xml
.....\..\design.cmp.bpm
.....\..\design.cmp.cdb
.....\..\design.cmp.hdb
.....\..\design.cmp.kpt
.....\..\design.cmp.logdb
.....\..\design.cmp.rdb
.....\..\design.cmp2.ddb
.....\..\design.cmp_merge.kpt
.....\..\design.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
.....\..\design.cycloneive_io_sim_cache.45um_ii_1200mv_0c_slow.hsd
.....\..\design.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd
.....\..\design.db_info
.....\..\design.fit.qmsg
.....\..\design.hier_info
.....\..\design.hif
.....\..\design.idb.cdb
.....\..\design.lpc.html
.....\..\design.lpc.rdb
.....\..\design.lpc.txt
.....\..\design.map.bpm
.....\..\design.map.cdb
.....\..\design.map.hdb
.....\..\design.map.kpt
.....\..\design.map.logdb
.....\..\design.map.qmsg
.....\..\design.map_bb.cdb
.....\..\design.map_bb.hdb
.....\..\design.map_bb.logdb
.....\..\design.pre_map.cdb
.....\..\design.pre_map.hdb
.....\..\design.root_partition.map.reg_db.cdb
.....\..\design.rtlv.hdb
.....\..\design.rtlv_sg.cdb
.....\..\design.rtlv_sg_swap.cdb
.....\..\design.sgdiff.cdb
.....\..\design.sgdiff.hdb
.....\..\design.sld_design_entry.sci
.....\..\design.sld_design_entry_dsc.sci
.....\..\design.smart_action.txt
.....\..\design.sta.qmsg
.....\..\design.sta.rdb
.....\..\design.sta_cmp.7_slow_1200mv_85c.tdb
.....\..\design.syn_hier_info
.....\..\design.tiscmp.fast_1200mv_0c.ddb
.....\..\design.tiscmp.slow_1200mv_0c.ddb
.....\..\design.tiscmp.slow_1200mv_85c.ddb
.....\..\design.tis_db_list.ddb
.....\..\design.tmw_info
.....\..\logic_util_heursitic.dat
.....\..\mux_foc.tdf
.....\..\mux_jib.tdf
.....\..\prev_cmp_design.map.qmsg
.....\..\prev_cmp_design.qmsg
.....\..\wed.zsf
.....\design.asm.rpt
.....\design.bdf
.....\design.cdf
.....\design.done
.....\design.fit.rpt
.....\design.fit.smsg
.....\design.fit.summary
.....\design.flow.rpt
.....\design.jdi
.....\design.map.rpt
.....\design.map.summary
.....\design.pin
.....\design.pof
.....\design.qpf
.....\design.qsf
.....\design.qws
.....\design.sof
.....\design.sta.rpt
.....\design.sta.summary
.....\design.tan.rpt
.....\design.tan.summary
.....\design.vwf
.....\design_assignment_defaults.qdf
    

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