Description: Design based on FPGA digital downconverter (DDC), the high-speed signal will be sampled baseband signal into a low rate for the next step in the signal processing. Is composed of four modules of the NCO, the digital mixer, the low pass filter and a decimation filter. Adder tree multiplier using self efficient multiplication.
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DDC_FPGA\17位有符号数相乘.txt
........\add-treetb.v
........\add_bx.v
........\add_bx.v.bak
........\add_bxfangyichu.v
........\add_bxfangyichu32.v
........\add_bxfangyichu36.v
........\add_tree.acf
........\add_tree.hif
........\add_tree.mmf
........\add_tree.v
........\b_y_trange.v
........\b_y_trange_18.v
........\bx_bx.v
........\bx_bx.v.bak
........\bxbx.v
........\clk_32.v
........\control.v
........\control_tb.v
........\control_tb.v.bak
........\data_in.v
........\data_in.v.bak
........\ddc.v
........\ddc_tb.v
........\ddc_test_tb.v
........\ddc_test_tb.v.bak
........\dds.v
........\dds.v.bak
........\dds_cos.v
........\dds_tb.v
........\dds_tb.v.bak
........\df128.v
........\df32.v
........\df512.acf
........\df512.v
........\df64.v
........\df8.v
........\df_test.v
........\df_test.v.bak
........\DFF.v
........\div24.v
........\FIR.cr.mti
........\fir.hif
........\FIR.mpf
........\FIR.v
........\FIR.v.bak
........\FIR_1.v
........\FIR_2.v
........\FIR_3.v
........\FIR_4.v
........\fir_tb.v
........\fir_tb.v.bak
........\fir_test_tb.v
........\fir_test_tb.v.bak
........\firDFF_16.v
........\firDFF_16_sample.v
........\firDFF_32_CLEAR.v
........\firDFF_32_CLEAR.v.bak
........\firDFF_32_CLEAR_rigion.v
........\firDFF_36_CLEAR.v
........\firtest_tb.v
........\h_rom.v
........\h_rom_1.v
........\h_rom_2.v
........\h_rom_3.v
........\h_rom_4.v
........\in.txt
........\Jieduan.v
........\Jieduan_18_16.v
........\Jieduan_32_16.v
........\Jieduan_32_28.v
........\Jieduan_32_29.v
........\Jieduan_36_16.v
........\Jieduan_rigion.v
........\multi16.v
........\multi16.v.bak
........\multi1616_29daifuhao.v
........\multi16_29daifuhao.v
........\multi16_32daifuhao.v
........\multi16_32daifuhao.v.bak
........\multi16_33daifuhao.v
........\multi16_region.v
........\multi17daifuhao.v
........\outputk.v
........\sine_rom.v
........\sine_sjcl.v
........\transcript
........\y_b_trange.v
........\y_b_trange_18.v
........\元件 dds.v
DDC_FPGA
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