Title:
CooperativeCommunication
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Description: 1. Decoding Principles of space-time block codes and algorithms 2. Study several different system model of cooperative diversity and cooperative diversity protocol 3 space-time block code codec and collaborative communication using the Verilog hardware description language to achieve ISE Integrated environment and comprehensive simulation results correctly downloaded to the FPGA circuit board observed with an oscilloscope output data is correct, verify empty block codes collaborative communication performance.
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File list (Check if you may need any files):
CooperativeCommunication\.lso
........................\addtou1.v
........................\addtou2.v
........................\chouqu1.v
........................\chouqu2.v
........................\chouqu3.v
........................\compxlib.cfg
........................\compxlib.log
........................\CooperativeCommunication.ise
........................\CooperativeCommunication.ise_ISE_Backup
........................\CooperativeCommunication.ntrc_log
........................\CooperativeCommunication.restore
........................\fenpin0.v
........................\fenpin1.v
........................\fircoe100K.coe
........................\geng1.v
........................\geng2.v
........................\hebing.v
........................\jiance1.v
........................\jiance2.v
........................\jiema.v
........................\jieshou.v
........................\jizhan.v
........................\lvbo1.v
........................\lvbo2.v
........................\lvbo3.v
........................\lvboqi.asy
........................\lvboqi.mif
........................\lvboqi.ngc
........................\lvboqi.sym
........................\lvboqi.v
........................\lvboqi.veo
........................\lvboqi.vhd
........................\lvboqi.vho
........................\lvboqi.xco
........................\lvboqi_flist.txt
........................\lvboqi_readme.txt
........................\lvboqi_xmdf.tcl
........................\M1.v
........................\M2.v
........................\malv1.v
........................\malv2.v
........................\model.list
........................\modelsim.ini
........................\netgen\translate\xitong_translate.nlf
........................\......\.........\xitong_translate.v
........................\power11.v
........................\power22.v
........................\power3.v
........................\qpsk1.v
........................\qpsk12.v
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........................\quzhen.v
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........................\shiftone.v
........................\shifttwo1.v
........................\shifttwo12.v
........................\shifttwo2.v
........................\shifttwo21.v
........................\stbc1.v
........................\stbc2.v
........................\templates\coregen.xml
........................\test_xitong.v
........................\test_xitong_v.fdo
........................\test_xitong_v.ndo
........................\test_xitong_v.udo
........................\transcript
........................\use1.v
........................\use2.v
........................\vsim.wlf
........................\work\glbl\verilog.asm
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........................\....\lvboqi\verilog.asm
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........................\....\malv1\verilog.asm
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........................\....\....2\verilog.asm
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........................\....\power11\verilog.asm
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........................\....\.....22\verilog.asm
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........................\....\.....3\verilog.asm
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........................\....\qpsk1\verilog.asm
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........................\....\.....2\verilog.asm
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........................\....\......\_primary.vhd
........................\....\....2\verilog.asm
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