程序代码\10\Aic23_top.mif
........\..\.udio_DAC_FIFO\cb_generator.pl
........\..\..............\class.ptf
........\..\..............\hdl\AUDIO_DAC_FIFO.v
........\..\..............\...\FIFO_16_256.v
........\..\Audio_Wave.bdf
........\..\sdaudionios.bsf
........\..\sd_audio_TOP.bdf
........\..\SD_Audio_TOP.bsf
........\..\software\sd_world\basic_io.h
........\..\........\........\hello_led.c
........\..\........\........\LCD.c
........\..\........\........\LCD.h
........\..\........\........\SD_Card.h
........\..\Verilog HDL Files\Aic23_top.v
........\..\.................\Audio_0.v
........\..\.................\AUDIO_DAC_FIFO.v
........\..\.................\audio_dac_fifo_0.v
........\..\.................\Audio_PLL.v
........\..\.................\AUDIO_WAVE.v
........\..\.................\counter.v
........\..\.................\cpu_0.v
........\..\.................\cpu_0_jtag_debug_module_sysclk.v
........\..\.................\cpu_0_jtag_debug_module_tck.v
........\..\.................\cpu_0_jtag_debug_module_wrapper.v
........\..\.................\cpu_0_mult_cell.v
........\..\.................\cpu_0_oci_test_bench.v
........\..\.................\cpu_0_test_bench.v
........\..\.................\div3.v
........\..\.................\epcs_flash_controller_0.v
........\..\.................\FIFO_16_256.v
........\..\.................\filter.v
........\..\.................\jtag_uart_0.v
........\..\.................\lcd_16207_0.v
........\..\.................\led_red.v
........\..\.................\Reset_Delay.v
........\..\.................\rom_day.v
........\..\.................\sdaudionios.v
........\..\.................\sdaudionios_clock_0.v
........\..\.................\sdaudionios_clock_1.v
........\..\.................\sdaudionios_inst.v
........\..\.................\sdram_0.v
........\..\.................\sdram_0_test_component.v
........\..\.................\SDRAM_PLL.v
........\..\.................\SD_Audio_TOP.v
........\..\.................\SD_Audio_TOP1.v
........\..\.................\SD_CLK.v
........\..\.................\SD_CMD.v
........\..\.................\SD_DAT.v
........\..\.................\seg_seven.v
........\..\.................\spi_clgen.v
........\..\.................\spi_defines.v
........\..\.................\spi_master.v
........\..\.................\spi_shift.v
........\..\.................\spi_top.v
........\..\.................\switch_pio.v
........\..\.................\timer_0.v
........\..\.................\timer_1.v
........\..\.................\timescale.v
........\.1\delay_reset_block.bdf
........\..\delay_reset_block.bsf
........\..\memorynios.bsf
........\..\memory_top.bdf
........\..\sd_pll.bsf
........\..\.oftware\flash_test_simple_0\flash_test_simple.c
........\..\........\hello_led_0\hello_led.c
........\..\SRAM\cb_generator.pl
........\..\....\class.ptf
........\..\....\hdl\SRAM.v
........\..\....\...\SRAM_hw.tcl
........\..\....\sram_16bit_512k.v
........\..\....\SRAM_16Bit_512K_hw.tcl
........\..\....\版权声明.txt
........\..\Verilog HDL Files\cpu_0.v
........\..\.................\cpu_0_jtag_debug_module_sysclk.v
........\..\.................\cpu_0_jtag_debug_module_tck.v
........\..\.................\cpu_0_jtag_debug_module_wrapper.v
........\..\.................\cpu_0_mult_cell.v
........\..\.................\cpu_0_oci_test_bench.v
........\..\.................\cpu_0_test_bench.v
........\..\.................\cpu_1.v
........\..\.................\cpu_1_jtag_debug_module_sysclk.v
........\..\.................\cpu_1_jtag_debug_module_tck.v
........\..\.................\cpu_1_jtag_debug_module_wrapper.v
........\..\.................\cpu_1_mult_cell.v
........\..\.................\cpu_1_oci_test_bench.v
........\..\.................\cpu_1_test_bench.v
........\..\.................\epcs_flash.v
........\..\.................\ext_sdram.v
........\..\.................\ext_sdram_test_component.v
........\..\.................\jtag_uart.v
........\..\.................\led_pio.v
........\..\.................\memorynios.v
........\..\.................\memorynios_inst.v
........\..\.....