rs_204_188 -  v1.0\altera_204_188.PNG
..................\RS_interleave.PNG
..................\rtl\RsDecodeSyndrome.v
..................\...\RsDecodeErasure.v
..................\...\RsDecodePolymul.v
..................\...\RsDecodeEuclide.v
..................\...\RsDecodeShiftOmega.v
..................\...\RsDecodeDegree.v
..................\...\RsDecodeChien.v
..................\...\RsDecodeInv.v
..................\...\RsDecodeDelay.v
..................\...\RsDecodeDpRam.v
..................\...\RsDecodeTop.v
..................\...\RsDecodeMult.v
..................\...\RsEncodeTop.v
..................\...\proj_rs.prj
..................\...\proj_rs.prd
..................\...\RsDecIn.hex
..................\...\RsDecOut.hex
..................\...\RsEncIn.hex
..................\...\RsEncOut.hex
..................\...\simReedSolomon.v
..................\...\IPSpecs.txt
..................\...\result.out
..................\...\RsEncodeTop.v.bak
..................\...\RsDecIn - 1_188.hex
..................\...\RsEncPack
..................\...\RsEncPack.v.bak
..................\...\simReedSolomon.v.bak
..................\...\RsDecodeTop.v.bak
..................\...\wave.do
..................\...\xilinx_primitive_ram.v
..................\...\Sim_RAM.v
..................\...\v5_stdram_lib
..................\...\v5_stdram_lib.v
..................\...\v5_stdram_lib.v.bak
..................\...\RsEncodePkg.v
..................\...\RsEncodePkg.v.bak
..................\...\xilinx_primitive_use_v5.v
..................\...\xilinx_primitive_use_v5.v.bak
..................\...\Sim_RAM.v.bak
..................\...\FPGA_Sel_Sim.v
..................\...\FPGA_Sel_Sim.v.bak
..................\...\rsdecode_pkg.v.bak
..................\...\RSDecodePkg.v
..................\...\rsdecodepkg.v.bak
..................\...\RsEncIn - 1-188_1s.hex
..................\...\RsDecIn - 1-188-1s.hex
..................\...\a.mem
..................\...\my_dec_in.txt
..................\...\my_dec_out.txt
..................\...\vsim.wlf
..................\...\rs_v1.0\run_options.txt
..................\...\.......\RsEncodeTop.tlg
..................\...\.......\RsEncodeTop.sap
..................\...\.......\RsEncodeTop.fse
..................\...\.......\RsEncodeTop.szr
..................\...\.......\AutoConstraint_RsEncodeTop.sdc
..................\...\.......\RsEncodeTop.srd
..................\...\.......\RsEncodeTop.srm
..................\...\.......\RsEncodeTop.map
..................\...\.......\RsEncodeTop.edf
..................\...\.......\synplicity.ucf
..................\...\.......\rpt_RsEncodeTop.areasrr
..................\...\.......\rpt_RsEncodeTop_areasrr.htm
..................\...\.......\traplog.tlg
..................\...\.......\.recordref
..................\...\.......\AutoConstraint_RsDecodeTop.sdc
..................\...\.......\rpt_RsDecodeTop.areasrr
..................\...\.......\rpt_RsDecodeTop_areasrr.htm
..................\...\.......\RsEncodeTop.srr
..................\...\.......\RsEncodeTop.srs
..................\...\.......\RsEncodeTop.ncf
..................\...\.......\FPGA_Sel.tlg
..................\...\.......\FPGA_Sel.sap
..................\...\.......\FPGA_Sel.fse
..................\...\.......\FPGA_Sel.szr
..................\...\.......\FPGA_Sel.srd
..................\...\.......\FPGA_Sel.srm
..................\...\.......\FPGA_Sel.map
..................\...\.......\FPGA_Sel.edf
..................\...\.......\RsEncodePkg.tlg
..................\...\.......\RsEncodePkg.srs
..................\...\.......\RsEncodePkg.sap
..................\...\.......\RsEncodePkg.fse
..................\...\.......\RsEncodePkg.szr
..................\...\.......\AutoConstraint_rsencode_pkg.sdc
..................\...\.......\RsEncodePkg.srd
..................\...\.......\RsEncodePkg.srm
..................\...\.......\RsEncodePkg.map
..................\...\.......\RsEncodePkg.edf
..................\...\.......\RsEncodePkg.ncf
..................\...\.......\rpt_rsencode_pkg.areasrr
..................\...\.......\rpt_rsencode_pkg_areasrr.htm
..................