Description: Verilog HDL language uart program, in others on the basis of changes and optimization is complete, quartus ii 10.0 compiler, integrated, on-board through simulation. The PC sends the string is sent back at once send multiple strings.
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uart_verilog\db\logic_util_heursitic.dat
............\..\prev_cmp_uart.qmsg
............\..\uart.amm.cdb
............\..\uart.analyze_file.qmsg
............\..\uart.asm.qmsg
............\..\uart.asm.rdb
............\..\uart.asm_labs.ddb
............\..\uart.cbx.xml
............\..\uart.cmp.bpm
............\..\uart.cmp.cbp
............\..\uart.cmp.cdb
............\..\uart.cmp.hdb
............\..\uart.cmp.kpt
............\..\uart.cmp.logdb
............\..\uart.cmp.rdb
............\..\uart.cmp_merge.kpt
............\..\uart.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
............\..\uart.cycloneive_io_sim_cache.45um_ii_1200mv_0c_slow.hsd
............\..\uart.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd
............\..\uart.db_info
............\..\uart.fit.qmsg
............\..\uart.hier_info
............\..\uart.hif
............\..\uart.idb.cdb
............\..\uart.lpc.html
............\..\uart.lpc.rdb
............\..\uart.lpc.txt
............\..\uart.map.bpm
............\..\uart.map.cbp
............\..\uart.map.cdb
............\..\uart.map.hdb
............\..\uart.map.kpt
............\..\uart.map.logdb
............\..\uart.map.qmsg
............\..\uart.map_bb.cdb
............\..\uart.map_bb.hdb
............\..\uart.map_bb.logdb
............\..\uart.pre_map.cdb
............\..\uart.pre_map.hdb
............\..\uart.rtlv.hdb
............\..\uart.rtlv_sg.cdb
............\..\uart.rtlv_sg_swap.cdb
............\..\uart.sgdiff.cdb
............\..\uart.sgdiff.hdb
............\..\uart.sld_design_entry.sci
............\..\uart.sld_design_entry_dsc.sci
............\..\uart.smart_action.txt
............\..\uart.sta.qmsg
............\..\uart.sta.rdb
............\..\uart.sta_cmp.7_slow_1200mv_85c.tdb
............\..\uart.syn_hier_info
............\..\uart.tiscmp.fast_1200mv_0c.ddb
............\..\uart.tiscmp.slow_1200mv_0c.ddb
............\..\uart.tiscmp.slow_1200mv_85c.ddb
............\..\uart.tis_db_list.ddb
............\..\uart.tmw_info
............\incremental_db\compiled_partitions\uart.db_info
............\..............\...................\uart.root_partition.cmp.cdb
............\..............\...................\uart.root_partition.cmp.dfp
............\..............\...................\uart.root_partition.cmp.hdb
............\..............\...................\uart.root_partition.cmp.kpt
............\..............\...................\uart.root_partition.cmp.logdb
............\..............\...................\uart.root_partition.cmp.rcfdb
............\..............\...................\uart.root_partition.cmp.re.rcfdb
............\..............\...................\uart.root_partition.map.cdb
............\..............\...................\uart.root_partition.map.dpi
............\..............\...................\uart.root_partition.map.hdb
............\..............\...................\uart.root_partition.map.kpt
............\..............\README
............\speed_select.v
............\uart.asm.rpt
............\uart.done
............\uart.dpf
............\uart.fit.rpt
............\uart.fit.smsg
............\uart.fit.summary
............\uart.flow.rpt
............\uart.map.rpt
............\uart.map.summary
............\uart.pin
............\uart.qpf
............\uart.qsf
............\uart.sof
............\uart.sta.rpt
............\uart.sta.summary
............\uart.v
............\uart.v.bak
............\uart_rx.v
............\uart_rx.v.bak
............\uart_tx.v
............\uart_tx.v.bak
............\incremental_db\compiled_partitions
............\db
............\incremental_db
uart_verilog
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