risc 4-way lru processor verilog\acc.v
................................\alu.v
................................\control.v
................................\ir.v
................................\mem.v
................................\mux12.v
................................\mux16.v
................................\pc.v
................................\bus_arbiter.v
................................\cmd_ack.v
................................\cmd_decoder.v
................................\cmd_detector.v
................................\cmd_generator.v
................................\cmd_internal_reg.v
................................\command_if.v
................................\data_cache_way0.v
................................\data_cache_way1.v
................................\data_cache_way2.v
................................\data_cache_way3.v
................................\data_in_reg.v
................................\data_port.v
................................\dma_cntrl.v
................................\dma_fifo.v
................................\dma_internal_reg.v
................................\uart.v~
................................\flash_ctrl.v
................................\fsm.v
................................\instruction_cache_way0.v
................................\instruction_cache_way1.v
................................\instruction_cache_way2.v
................................\instruction_cache_way3.v
................................\k9f1g08u0m.v
................................\lru_data_cache.v
................................\lru_instruction_cache.v
................................\oe_generator.v
................................\parameter.v
................................\ras_cas_delay.v
................................\ref_ack.v
................................\ref_timer.v
................................\risc.v
................................\sdram_cntrl.v
................................\sdram_mux.v
................................\sdram_port.v
................................\sdramctrl_rtl.v
................................\REadme~
................................\REadme
................................\soc.v
................................\timer.v
................................\uart.v
risc 4-way lru processor verilog