synplifyPro_examples\basic_flow\src\ALU.V
....................\..........\...\HDL_DEMO.V
....................\source\mixed\verilog\mux.vhd
....................\......\.....\.......\mux21.v
....................\......\.....\.......\reg8.vhd
....................\......\.....\.......\rotate.vhd
....................\......\.....\.......\top.v
....................\......\.....\.hdl\mux.v
....................\......\.....\....\mux21.vhd
....................\......\.....\....\reg8.v
....................\......\.....\....\rotate.v
....................\......\.....\....\top.vhd
....................\......\verilog\ALU.V
....................\......\.......\HDL_DEMO.V
....................\......\VHDL\ALU.VHD
....................\......\....\HDL_DEMO.VHD
....................\......\mixed\verilog
....................\......\.....\vhdl
....................\basic_flow\src
....................\..........\syn
....................\source\mixed
....................\......\verilog
....................\......\VHDL
....................\basic_flow
....................\source
synplifyPro_examples