Welcome![Sign In][Sign Up]
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: dgnszsz Download
 Description: Multifunctional digital clock in quartusII software platform to achieve the verilog source code. We try.
 Downloaders recently: [More information of uploader 廖飞]
 To Search:
File list (Check if you may need any files):
 

多功能数字钟
............\clock.asm.rpt
............\clock.done
............\clock.fit.rpt
............\clock.fit.smsg
............\clock.fit.summary
............\clock.flow.rpt
............\clock.map.rpt
............\clock.map.summary
............\clock.pin
............\clock.pof
............\clock.qpf
............\clock.qsf
............\clock.qws
............\clock.sof
............\clock.tan.rpt
............\clock.tan.summary
............\clock.v
............\db
............\..\clock.asm.qmsg
............\..\clock.asm_labs.ddb
............\..\clock.cbx.xml
............\..\clock.cmp.cdb
............\..\clock.cmp.hdb
............\..\clock.cmp.kpt
............\..\clock.cmp.logdb
............\..\clock.cmp.rdb
............\..\clock.cmp.tdb
............\..\clock.cmp0.ddb
............\..\clock.cmp2.ddb
............\..\clock.db_info
............\..\clock.dbp
............\..\clock.eco.cdb
............\..\clock.fit.qmsg
............\..\clock.hier_info
............\..\clock.hif
............\..\clock.map.cdb
............\..\clock.map.hdb
............\..\clock.map.logdb
............\..\clock.map.qmsg
............\..\clock.pre_map.cdb
............\..\clock.pre_map.hdb
............\..\clock.psp
............\..\clock.rtlv.hdb
............\..\clock.rtlv_sg.cdb
............\..\clock.rtlv_sg_swap.cdb
............\..\clock.sgdiff.cdb
............\..\clock.sgdiff.hdb
............\..\clock.signalprobe.cdb
............\..\clock.sld_design_entry.sci
............\..\clock.sld_design_entry_dsc.sci
............\..\clock.syn_hier_info
............\..\clock.tan.qmsg
    

CodeBus www.codebus.net