Description: FPGA-based UART program design, VERILOG HDL language, enabling serial communication baud rate to 115200. Has been verified through the serial debugging assistant.
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File list (Check if you may need any files):
uart
....\baud.bsf
....\baud.v
....\db
....\..\logic_util_heursitic.dat
....\..\prev_cmp_uart.qmsg
....\..\uart.amm.cdb
....\..\uart.asm.qmsg
....\..\uart.asm.rdb
....\..\uart.asm_labs.ddb
....\..\uart.cbx.xml
....\..\uart.cmp.bpm
....\..\uart.cmp.cdb
....\..\uart.cmp.hdb
....\..\uart.cmp.kpt
....\..\uart.cmp.logdb
....\..\uart.cmp.rdb
....\..\uart.cmp0.ddb
....\..\uart.cmp1.ddb
....\..\uart.cmp2.ddb
....\..\uart.cmp_merge.kpt
....\..\uart.db_info
....\..\uart.eda.qmsg
....\..\uart.fit.qmsg
....\..\uart.hier_info
....\..\uart.hif
....\..\uart.idb.cdb
....\..\uart.lpc.html
....\..\uart.lpc.rdb
....\..\uart.lpc.txt
....\..\uart.map.bpm
....\..\uart.map.cdb
....\..\uart.map.hdb
....\..\uart.map.kpt
....\..\uart.map.logdb
....\..\uart.map.qmsg
....\..\uart.map_bb.cdb
....\..\uart.map_bb.hdb
....\..\uart.map_bb.logdb
....\..\uart.pre_map.cdb
....\..\uart.pre_map.hdb
....\..\uart.root_partition.map.reg_db.cdb
....\..\uart.rpp.qmsg
....\..\uart.rtlv.hdb
....\..\uart.rtlv_sg.cdb
....\..\uart.rtlv_sg_swap.cdb
....\..\uart.sgate.rvd
....\..\uart.sgate_sm.rvd
....\..\uart.sgdiff.cdb
....\..\uart.sgdiff.hdb
....\..\uart.sld_design_entry.sci
....\..\uart.sld_design_entry_dsc.sci
....\..\uart.smart_action.txt
....\..\uart.sta.qmsg
....\..\uart.sta.rdb
....\..\uart.sta_cmp.8_slow.tdb
....\..\uart.syn_hier_info
....\..\uart.tis_db_list.ddb
....\..\uart.tmw_info
....\incremental_db
....\..............\compiled_partitions
....\..............\...................\uart.db_info
....\..............\...................\uart.root_partition.cmp.cdb
....\..............\...................\uart.root_partition.cmp.dfp
....\..............\...................\uart.root_partition.cmp.hdb
....\..............\...................\uart.root_partition.cmp.kpt
....\..............\...................\uart.root_partition.cmp.logdb
....\..............\...................\uart.root_partition.cmp.rcfdb
....\..............\...................\uart.root_partition.map.cdb
....\..............\...................\uart.root_partition.map.dpi
....\..............\...................\uart.root_partition.map.hbdb.cdb
....\..............\...................\uart.root_partition.map.hbdb.hb_info
....\..............\...................\uart.root_partition.map.hbdb.hdb
....\..............\...................\uart.root_partition.map.hbdb.sig
....\..............\...................\uart.root_partition.map.hdb
....\..............\...................\uart.root_partition.map.kpt
....\..............\README
....\rec.bsf
....\rec.v
....\send.bsf
....\send.v
....\simulation
....\..........\modelsim
....\..........\........\modelsim.ini
....\..........\........\msim_transcript
....\..........\........\rtl_work
....\..........\........\........\baud
....\..........\........\........\....\verilog.prw
....\..........\........\........\....\verilog.psm
....\..........\........\........\....\_primary.dat
....\..........\........\........\....\_primary.dbs
....\..........\........\........\....\_primary.vhd
....\..........\........\........\rec
....\..........\........\........\...\verilog.prw
....\..........\........\........\...\verilog.psm
....\..........\........\........\...\_primary.dat
....\..........\........\........\...\_primary.dbs
....\..........\........\........\...\_primary.vhd
....\..........\........\........\send
....\..........\........\........\....\verilog.prw
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