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Title: mini_aes_latest.tar Download
 Description: It is minimal version of AES verilog implementation. It is really simple and easy to understaning.. works well manual included. Enjoy!
 Downloaders recently: [More information of uploader Ho Joon Lee]
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mini_aes\branches
........\tags\INITIAL\bench\devel.do
........\....\.......\.....\input.vhdl
........\....\.......\.....\modelsim_bench.do
........\....\.......\.....\modelsim_bench.vhdl
........\....\.......\.....\output.vhdl
........\....\.......\data\ecb_tbl.txt
........\....\.......\....\xilinx_fpga.ucf
........\....\.......\.oc\acrobat_view
........\....\.......\...\aes128block.eps
........\....\.......\...\area.eps
........\....\.......\...\circuit_schematic.eps
........\....\.......\...\ganesha.ps
........\....\.......\...\key_scheduler.eps
........\....\.......\...\Makefile
........\....\.......\...\mini_aes.pdf
........\....\.......\...\mini_aes.tex
........\....\.......\...\oc_logo.eps
........\....\.......\README
........\....\.......\source\bram_block_a.vhdl
........\....\.......\......\bram_block_b.vhdl
........\....\.......\......\counter2bit.vhdl
........\....\.......\......\folded_register.vhdl
........\....\.......\......\key_scheduler.vhdl
........\....\.......\......\mini_aes.vhdl
........\....\.......\......\mix_column.vhdl
........\....\.......\......\xtime.vhdl
........\.runk\bench\input.vhdl
........\.....\.....\modelsim_bench.do
........\.....\.....\modelsim_bench.vhdl
........\.....\.....\output.vhdl
........\.....\data\ecb_tbl.txt
........\.....\....\xilinx_fpga.ucf
........\.....\.oc\acrobat_view
........\.....\...\aes128block.eps
........\.....\...\area.eps
........\.....\...\circuit_schematic.eps
........\.....\...\key_scheduler.eps
........\.....\...\Makefile
........\.....\...\mini_aes.pdf
........\.....\...\mini_aes.tex
........\.....\...\oc_logo.eps
........\.....\LICENSE.txt
........\.....\README
........\.....\source\bram_block_a.vhdl
........\.....\......\bram_block_b.vhdl
........\.....\......\counter2bit.vhdl
........\.....\......\folded_register.vhdl
........\.....\......\io_interface.vhdl
........\.....\......\key_scheduler.vhdl
........\.....\......\mini_aes.vhdl
........\.....\......\mix_column.vhdl
........\.....\......\xtime.vhdl
........\web_uploads
    

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