- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 10kb
- Update:
- 2013-10-04
- Downloads:
- 0 Times
- Uploaded by:
- WPI
Description: This a simple example of FIFO (first in and first out) module written in verilog code
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FIFO.docx