Description: The full version of the VHDL design CPU VHDL experimental procedures and downloaded to the experimental stage, the program may have some small errors need to adjust the values, computing, deposits, write back and control several modules
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File list (Check if you may need any files):
intheend\aaa
........\aaa.BAK
........\main\calculate.fdo
........\....\calculate.udo
........\....\calculate.vhd
........\....\clock.vhd
........\....\clock_bencher.prj
........\....\ctrl.vhd
........\....\device_usage_statistics.html
........\....\director.vhd
........\....\main\calculate.vhd
........\....\....\clock.vhd
........\....\....\ctrl.vhd
........\....\....\director.vhd
........\....\....\main.bgn
........\....\....\main.bit
........\....\....\main.bld
........\....\....\main.cel
........\....\....\main.cmd_log
........\....\....\main.drc
........\....\....\main.ise
........\....\....\main.ise_ISE_Backup
........\....\....\main.lfp
........\....\....\main.lso
........\....\....\main.ncd
........\....\....\main.ngc
........\....\....\main.ngd
........\....\....\main.ngr
........\....\....\main.ntrc_log
........\....\....\main.pad
........\....\....\main.par
........\....\....\main.pcf
........\....\....\main.prj
........\....\....\main.stx
........\....\....\main.syr
........\....\....\main.twr
........\....\....\main.twx
........\....\....\main.ucf
........\....\....\main.unroutes
........\....\....\main.ut
........\....\....\main.vhd
........\....\....\main.xpi
........\....\....\main.xst
........\....\....\main_guide.ncd
........\....\....\main_map.map
........\....\....\main_map.mrp
........\....\....\main_map.ncd
........\....\....\main_map.ngm
........\....\....\main_pad.csv
........\....\....\main_pad.txt
........\....\....\main_prev_built.ngd
........\....\....\main_summary.html
........\....\....\main_summary.xml
........\....\....\main_usage.xml
........\....\....\main_vhdl.prj
........\....\....\memory.vhd
........\....\....\pepExtractor.prj
........\....\....\results.txt
........\....\....\transcript
........\....\....\vsim.wlf
........\....\....\wave.ant
........\....\....\WAVE.fdo
........\....\....\wave.jhd
........\....\....\WAVE.tbw
........\....\....\WAVE.udo
........\....\....\wave.vhw
........\....\....\wave.xwv
........\....\....\WAVE.xwv_bak
........\....\....\WAVE_bencher.prj
........\....\....\work\calculate\behavioral.dat
........\....\....\....\.........\behavioral.psm
........\....\....\....\.........\_primary.dat
........\....\....\....\.lock\behavioral.dat
........\....\....\....\.....\behavioral.psm
........\....\....\....\.....\_primary.dat
........\....\....\....\.trl\behavioral.dat
........\....\....\....\....\behavioral.psm
........\....\....\....\....\_primary.dat
........\....\....\....\director\behavioral.dat
........\....\....\....\........\behavioral.psm
........\....\....\....\........\_primary.dat
........\....\....\....\main\behavioral.dat
........\....\....\....\....\behavioral.psm
........\....\....\....\....\_primary.dat
........\....\....\....\.emory\behavioral.dat
........\....\....\....\......\behavioral.psm
........\....\....\....\......\_primary.dat
........\....\....\....\wave\testbench_arch.dat
........\....\....\....\....\testbench_arch.psm
........\....\....\....\....\_primary.dat
........\....\....\....\.riteback\behavioral.dat
........\....\....\....\.........\behavioral.psm
........\....\....\....\.........\_primary.dat
........\....\....\....\_info
........\....\....\writeback.vhd
........\....\....\xst\dump.xst\main.prj\ntrc.scr
........\....\....\...\work\hdllib.ref
........\....\....\...\....\hdpdeps.ref
........\....\....\...\....\sub00\vhpl00.vho
........\....\....\...\....\.....\vhpl01.vho
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